Lab 7: Using Busses and Arrays in the Desing of Word Inverters, Muxes, and High-Speed Adders - EE 421L     

Authored By: Joey Yurgelon

Email: yurgelon@unlv.nevada.edu

October 21st, 2015

  

Pre-lab Work:

 Exercise #1: Draft, Simulate, and Layout a 31 stage ring oscillator. Make sure that the device is DRC and LVS clean.

   

   
Lab Description:

Lab Requirements:
     

Experimental Results: 

      

    Exercise #1: Show, in your lab report, how a capacitive load influences the delay and rise/fall times of the inverter array.


 
    Exercise #2: Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates. Provide a few simulation examples using these gates.

Gates Driven with a 100fF Capacitive Load

Gates Driven with a 1pF Capacitive Load

      

 Exercise #3: Draft the schematic of a 2-to-1 DEMUX/MUX and explain how it works in both configurations using spectre. Create an 8-bit wide version with only a single 'Select' input. 



   

 Exercise #4: Draft the full-adder schematic seen in Fig. 12.20. Layout, simulate, and produce a 8-bit adder cell. 

   

 
 

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