Project - EE 421L 

Vrigiank@unlv.nevada.edu

Kirk Vrigian

11/6/15

Lab description

    The final project includes the schematics and simulations of the following circuits:
 

Lab procedure:

25K Resistor

Below are the schematic, symbol, simulation circuit & corresponding simulation results.


25K Resistor schematic
http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/25k_resistor.JPG

25K Resistor symbol (using create from cellview)

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/25k_symbol.JPG

Simulation Circuit (along with simulation parameters).
    By sweeping the voltage source (using dc sweep analysis) from 0-5 volts we can verify that the 25k resistor is working by comparing the linear relationship V=IR

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/25k_resistor_schematic_simulation.JPG

Simulation Results
    The results support our linear relationship of a 25k resistor. At 5V we get an I of 200uA.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/25k_simulation_results.JPG


Voltage Divider:

Next, create a voltage divider utilizing a 25k resistor followed by a 10k resistor. Like before, create a 10k resistor & corresponding symbol.

Schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/10k_res_schematic.JPG

Symbol

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/10k_symbol.JPG

Now to create the voltage divider schematic, symbol & finally the test schematic utilizing the voltage divider symbol.

Schematic for voltage divider

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/25k_10k_voltage_divider_schematic.JPG

Corresponding voltage divider symbol

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/25k_10k_voltage_divider_symbol.JPG

Simulation schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/25k_10k_voltage_divider_schematic_sim.JPG

Simulation results (transient response of 1 nano).
    Using an input of 5V, the expected output is 5*(10K)/(10K+25K) = 1.429V. The simulation confirms the voltage divider is working properly.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/25k_10k_vdivider_results.JPG

NMOS Transistor:

Below is the schematic, symbol & IV characteristic curves for a 6u/.6u NMOS transistor.

NMOS schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/nmos_IV_schematic.JPG

Simulation circuit using symbol (created from cellview)

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/NMOS_sim_schematic_1.JPG

ID vs. VDS (sweeping VGS from 0-5 & VDS from 0-5 using a parametric analysis)

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/NMOS_curves.JPG

2nd simulation schematic for the same NMOS

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/NMOS_sim_schematic_2.JPG

This time it's ID vs. VGS and leaving VDS at 100mV.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/nmos_curve_2.JPG

Now for the PMOS transistor

 Below is the schematic, symbol along with IV characteristic curves for a 6u/.6u PMOS transistor.

PMOS_IV Schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/pmos_IV_schematic.JPG

PMOS_IV simulation schematic using corresponding symbol

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/Pmos_sim_schematic_1.JPG

Again, using this schematic and using parametric analysis, one can generate ID vs. VSD by stepping VSG

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/PMOS_curves.JPG

2nd PMOS_IV simulation schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/pmos_sim_schematic_2.JPG

ID vs. VSG (using a vds of 100m & sweeping vsg from 0-5V)

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/PMOS_sim_results_2.JPG

Inverter with 6u/.6u NMOS & 12u/.6u PMOS

Below is the schematic & simulation for the 12u/6u inverter.

Schematic of 12u/6u inverter

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/inverter_schematic.JPG

Simulation schematic of 12u/6u inverter (using symbol created from cellview)

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/inverter_sim_schematic.JPG

Doing a dc sweep from 0-5V of IN will result in the following results, showing that our inverter is working properly. The point the at which /in & /out instersect is our VSP.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/inverter_results.JPG


NAND/NOR gate utilizing 6u/.6u transistors

NAND gate schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/nand_schematic.JPG

6u/6u NOR schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/nor_schematic.JPG

6u/6u NAND/NOR simulation schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/nand_nor_sim_schematic.JPG

6u/6u  NAND/NOR simulation results

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/nand_nor_results.JPG

The simulation of the two gates consisted of feeding all 4 possible logic combinations of the inputs to each gate (00,01,10,11). The results are as expected, the only time that the NAND output is low is when both input signals are high and the only time that the NOR gate output is high is when both inputs are low.

31 Stage Oscillator

Below is the schematic & simulation of a 31 stage ring oscillator with an output buffer driving a 20pF load. The inverters outside the inverter array (using an A multiplier of 8 & a stage of m=64) are used as an output buffer so that the oscillator can drive a 20pF load.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/osc_schematic.JPG


Oscillator simulation schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/osc_sim_schematic.JPG

From the simulation one can see that period of the oscillator is roughly 5ns, which translates to a frequency of  200Mhz  (T=1/f).

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/osc_results.JPG

8-bit Resettable Up/Down Counter:

 The basic building block of a Resettable Up/Down counter is a D flip flop with a clear. Below are the pictures showing a D flip flop with a clear and the simulations.

Schematic of a resettable D-FF

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/D_FF_schematic.JPG

D-FF simulation schematic

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/D_FF_sim_schematic.JPG

Simulation results (showing clear when high & low)

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/D_FF_results.JPG

 Below are pictures showing the schematic of an up/down counter utilizing the D-FF & transmission gates.

1-bit up/down counter

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/up_down_counter_1_bit.JPG

8-bit up/down counter

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/up_down_counter_8_bit.JPG


To go from a single bit up/down counter to the 8 bit counter, simply create a symbol for the 1 single bit. Then use the 1-bit counter symbol & modify it's properties to have an array from <0:7>. Then by using buses, connect wires to the right locations by using proper labeling of the buses. Then you can simply create a symbol of the 8-bit counter for testing.
The functionality of the up/down counter is that when an input with signal high (VDD)  is fed into the up input, the counter will count up. When a input signal low (GND) is fed into the up input, the counter will count down. Also whenever a low is fed into the CLR, the counter will clear all it's registers to 0 and start up or down counting from 0 once the CLR signal goes back to high.

8-bit counter counting down from 255 to 0.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/counting_down.JPG

8-bit counter counting up to 255.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/counting_up.JPG

Counting up with clear

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/counting_clear.JPG

Below are the layouts to the cells shown above.

Voltage divider

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/volt_divider.JPG

NMOS

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/NMOS.JPG

PMOS

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/PMOS_IV.JPG

Inverter 12u/6u

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/inverter.JPG

NAND

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/nand.JPG

NOR

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/nor.JPG

Ring oscillator with 20pF buffer

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/oscillator_buffer.JPG

D Flip Flop

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/D_FF.JPG

1 bit counter

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/counter.JPG

8-bit counter including up/down

http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/layout_images/counter_8_bit.JPG



All of the files for this lab can be found here.

Be sure to backup all your lab by uploading it to a drive or online.


http://cmosedu.com/jbaker/courses/ee421L/f15/students/vrigiank/proj/images/upload.JPG














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