Lab 7 - ECE 421L 

Authored by Giang Tran

10/28/2015

trang@unlv.nevada.edu

 

Lab description:

Pre-Lab

31 stage Ring oscillator is made by placing 31 inverters horizontally with the final output feeding back into our first input. 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre1.PNG

We'll get the following waveform

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre2.PNG

31 stage ring oscillator looks long and complicated if we draft it one by one. This can be fixed by using an array of 31 inverters. 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre3.PNG

Adding thick wires to input and output.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre4.PNG

Add the following labels to input and output nodes.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre5.PNG

Check and Save, then run the simulation.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre6.PNG

Ring oscillator layout view.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre7.PNG

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre8.PNG

extracted view

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre9.PNG

layout view

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre10.PNG

DRC and LVS, LVS fail because we did not create an output pin for our schematic.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre11.PNG

Adding output pin osc_out to schematic.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre12.PNG

LVS match!

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre13.PNG

Create a cellview for our ring oscillator. Then draft the following circuit.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre15.PNG

Run the simulation, we should get something very similar to our previous waveforms.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre16.PNG

Extracted view simulation

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre17.PNG

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/pre18.PNG

Post-Lab

Drafting a 6u/0.6u inverter.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post1.PNG

We'll make our 4 bits inverter using the method in our prelab.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post2.PNG

Create a symbol for our 4-bit inverter

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post3.PNG

Simulate our 4-bit inverter driving 3 different size capacitors. Use the following schematic.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post4.PNG

Our transient response is as following. We can see that if our input is low then our output is high, 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post5.PNG

8-bit NAND gate

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post6_nand.PNG

8-bit NAND gate symbol

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post7.PNG

Schematic to simulate our 8-bit NAND gate

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post8.PNG

We'll get the following response


http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post9.PNG

8-bit AND gate can be made easily by adding an inverter to our NAND output.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post10_and.PNG

Creating symbol view

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post11.PNG

Draft the following circuit to test our 8-bit AND gate. Note that since NAND is the inverted version of AND; hence, our output is the opposite of the previous circuit.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post12.PNG

Transient response

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post13.PNG

Drafting a NOR circuit

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post14_nor.PNG

Symbol of our NOR gate.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post15.PNG

Drafting our 8-bit NOR gate

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post16.PNG

8-bit NOR gate symbol

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post17.PNG

Draft the following circuit to simulate our 8-bit NOR gate

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post18.PNG

Here's a table for 2 input NOR gate. We'll expect similar response for our output.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post19.jpg
http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post20.PNG

To get an OR gate, we'll add an inverter to the output of our XOR gate.


http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post21.PNG

Create a symbol for our circuit.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post22.PNG

Drafting a 8-bit OR gate

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post23.PNG

8-bit OR gate symbol

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post24.PNG

Draft the following circuit to test our 8-bit OR gate

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post25.PNG

Transient Response

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post26.PNG

Drafting a 8-bit inverter

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post27_inverter.PNG

Symbol

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post28.PNG

Draft the following circuit to test our 8-bit inverter.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post29.PNG

Transient Response

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post30.PNG

Next up, we'll begin the design of our 2-bit MUX. Draft the following circuit

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post31_MUX.PNG

The operation of our MUX is as the following:
 -When S is high (1) then Si is low (0)
     -The NMOS and PMOS connected to A are turned on causing the output to go to A.
     -The PMOS and NMOS connected to B are turned off.
-When S is low (0) then Si is high (1)
     -The NMOS and PMOS connected to B are turned on causing the output to go to B.
     -The PMOS and NMOS connected to A are turned off.
Create a symbol for our circuit.


http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post32.PNG

Sim our MUX to get the following response.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post33.PNG

To create our 8-bit MUX without the inverted S terminal, we'll reuse the existing schematic of our MUX to speed thing up. We'll connect the S terminal to the Si terminal through an inverter. That is if S is high then Si is low (inverted). Note that we'll need a 8-bit inverter for it to work.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post34.PNG

Create a symbol for our 8-bit MUX.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post35.PNG

Draft the following circuit to test our 8-bit MUX

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post36.PNG

Transient Response

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post37.PNG

Fulladder design

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post38.PNG

Symbol view

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post39.PNG

Draft the following schematic to test our fulladder.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post40.PNG

Transient Response

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post41.PNG

Making a 80bit fulladder

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post42.PNG

8-bit fulladder symbol

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post43.PNG

8-bit fulladder testing

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post44.PNG

We'll get the following response

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post45.PNG

We'll begin the design of our fulladder. Let's start our with 1-bit fulladder

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post46.PNG

Make sure there are enough room in between so we can easily connect the wires. DRC and LVS check after finish.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post47.PNG

Let us run the simulation again using our extracted layout to verify it matches our schematic response.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post48.PNG

Verified!

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post49.PNG

Laying out our 8-bit fulladder

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post50.PNG

LVS match!

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post51.PNG

Here's how I connect my 8-bit fulladder bit-by-bit. At the first bit:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post52.PNG

At the last bit:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post53.PNG

Run our simulation again using our extracted view.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post54.PNG

It is verified that we obtain similar result using our extracted view.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab7/postlab/post55.PNG

I've used 6 different capacitor values in very single one of our 8-bit simulations with noticeable differences. The smallest capacitor will gives us the near perfect output, while the largest capacitor barely able to discharge. This is because the time delay for the lower value capacitors is low since T(delay) = 0.7*R*C, hence, small C results in small time delay. We can keep it simple by treating the capacitors as buckets. Smaller buckets require less time to fill and empty. While the bigger buckets require more time to fill and empty. Our 1nF capacitor sometimes did not have to enough time to discharge then the next cycle kicks in and fill it back up.


Saving My Work!!!

All files and images are backed up in a folder on my desktop,


I'll then send a copy to my email as a backup. 

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