Lab X - ECE 421L
-Design, layout, and simulation of a CMOS inverter.
-Going through Tutorial 3
Pre-lab
-We'll start off by making a new library called Lab5 then create a new schematic. We'll instantiate our 6 um by 600 nm NMOS and our 12 um by 600 nm PMOS in the previous lab. We'll add vdd to our source terminal in our PMOSand ground our source terminal on NMOS. Name our input terminal A and output terminal Ai like below.
Connecting the terminal using metal1 and poly. Notice, our input terminal is connected to the poly of M1_POLY, PMOS and NMOS using a poly layer.
DRC our layout, make sure there's no error. After DRC check, we can proceed and extract our layout view of the inverter.
Run LVS, make sure our net-list match.
.
Going back to our library, we'll create a new schematic called sim_inverter.
Add the following circuit to our sim_inverter.
Remember to check and save our circuit. Next, we'll go to ADE then set up our simulation like below.
Go to Output >> To be plotted >> On schematic. Select input and out.
Run the simulation, we'll get something similar to this.
Notice that our Vout is at 0 V. This is because we did NOT specify a value for VDD.
Going back to our Sim_Inverter, we'll instantiate a vdd with 5 V.
Check and save our circuit, then run the simulation again. We'll get something similar to below.
Next up, let's simulate our circuit using the extracted layout of our inverter.
Add extracted in front of schematic in Setup -> Environment.
Click run, we'll get an identical waveform as above
Post-Lab
Again, we're asked to build an inverter with 6 um by 600 nm NMOS and 12 um by 600 nm PMOS. It is easier to copy and paste our inverter from the prelab to a new schematic.
We'll get an identical circuit
12u/6u 48u/24u
Next up, we'll LVS our extracted view making sure all pins match!
Simulations
12u/6u inverter simulation without UltraSim
100f F 100p F
10p F 1p F
48u/24u inverter without UltraSim
100f F 100p F
10p F 1p F
Conclusion: We know that capacitors charge over time, and bigger capacitor requires more time to charge. Therefore, we can see that with a relatively small capacitor, 100f F, the capacitor charges up to 5 V then discharges as the pulse goes back down to 0 V. As we increase the capacitor size from 100f F to 100p F, the capacitor didn't have enough time to fully charged to 5 V then discharged resulting in a sine wave looking response. This can be seen better for 10p F and 1p F capacitors, the response is nearly a straight line. This is because the capacitors did not have sufficient amount of time to either charge or discharge.
-The inverter was setup so that if A (input) is at 5 V (1). It will turns on our NMOS and output 0 V to Ai. This is because our NMOS is connected to ground, meanwhile, our PMOS stays off (0) because it is inverted. When A is at 0 V (0). Our NMOS is OFF and PMOS is ON; hence, Ai will have an output value of VDD.
Simulation with UltraSim
12u/6u
I'll then send a copy to my email as a backup.
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