Lab 4 - ECE 421L 

Authored by Giang Tran

9/18/2015

trang@unlv.nevada.edu

 

Lab description:

-Layout and simulate the operation of NMOS and PMOS using the C5 process.
-Add bonding pads to NMOS and PMOS terminals
Pre-Lab
-First, we'll create a schematic and layout for our NMOS device in a new library called Tutorial_2. Create an instance called nmos in NCSU_Analog_Parts window. Our NMOS will have a width of 6u M and a length of 600n M.
-Next is to add pins according to below.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/1.PNG

-Always making sure to run DRC before proceeding to the next step.
-We'll create a symbol for the circuit above, click on Create > Cell View > From Cell View. We'll be drawing a symbol for the circuit so its neccessary to delete everything except for the 3 pins. Draw a symbol like below.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/2.PNG

-Next, create a new schematic call sim_NMOS_IV_3
-Add components and wire up the circuit like below

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/3.PNG

-We will be simulating the circuit using Parametric Analysis

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/4_parametric.PNG

-Our waveform will look similar to this

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/5_simulation.PNG

-Close all tabs, we'll make a new layout cell call NMOS_IV_3
-Create an instance called nmos in the NCSU_TechLib_ami06 library. Again, the length is 600n M and width is 6u M. Next instantiate a a ptap cell (metal1 to p+ connection) and a metal1 to poly cell connection line below.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/6_poly_m1.PNG

-Again, DRC your layout making sure it has no error.
-Extract the layout

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/7_extracted.PNG

-Although DRC shows no error but LVS cannot match up the netlist!

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/8_error.PNG

-This is because if we look closely at our extracted layout view we'll see pin #4 on the NMOS is missing connection.
-Fix up our layout by adding a pin with global variable gnd! in the ptap cell.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/9_newlayout.PNG

-Look at our new extracted layout view, we'll see the middle pin now is referenced to ground.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/10_newextracted.PNG

-Although, all pins have connection but LVS wants us to use a 4 legs NMOS instead of 3 legs.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/11_error.PNG

-Go back  to the NMOS_IV_3 schematic, we'll place the nmos with nmos4.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/12_newschem.PNG

-Run LVS with our new schematic. Netlist match!

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/13_match.PNG

-We'll run our simulation again using extracted view. Go to Setup > Environment. Then put extracted in front of schematic.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/14_sim.PNG

-Run our Parametric Simulation again

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/15_waveform.PNG

-Next up, we'll create our PMOS using pmos from NCSU_Analog_Parts.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/16_pmos.PNG

-Create a symbol just like our NMOS.
-Creating a new cell layout call PMOS_IV. We'll instantiating the following layout. Our components below are pmos, ptap, and metal1 to poly connection.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/17_extracted.PNG

-Check and Save make sure no error is found. We'll make an extracted layout view for the layout.
-Next up, let's create a cell call sim_PMOS_IV. Create the following circuit.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/18_schem.PNG

-Run our simulation with schematic view of circuit.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/19_withoutextract.PNG

-Next, we want to run simulation again with extracted layout.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/20_withextract.PNG

Our 2 simulation results look identical to each other!


Post Lab
http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post1.PNG

-We'll be using parametric analysis for analyzing the circuit. Set up dc analysis with VDS varies from 0 to 5 V with 1 mV steps. We then define a new variable for VGS with a value of 0 V. Make sure we're plotting the current at drain like the picture below.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post2.PNG

Doing a parametric analysis with VGS from 0 to 5 V ata linear step of 1 V. We'll get a waveform similar to below.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post3.PNG


http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post4.PNG

-Notice our V0 is at 0 V and V1 = VDS.
-Again, we're doing dc analysis with V0 varies from 0 to 2 V with a linear step of 1 mV. Define a new variable name VDS with value of 100 mV and plot the current at drain. We'll run a parametric analysis on the circuit and get the following response.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post6.PNG


http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post7.PNG

Set up the analysis like below

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post8.PNG

We'll the following response:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post9.PNG


http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post10.PNG

After setting up the analysis parameters, we'll get the following response:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post11.PNG


-We can use our bond pad created from previous Tutorial_6, but I went ahead and create a new pad layout to refresh my memory.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post14.PNG

 After the pad is created, I went ahead and connect the NMOS device terminals to 4 different pads.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post12.PNG

We'll ensure the connections of metal1, metal2, and metal3 are perfect by having multiple via(s) in 1 connection. We definitely want bigger wires as safety for electromigration.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post13.PNG

Remember to DRC check everytime we made a new metal connection. I found it time consuming by fixing the design rules of spacing.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post15_DRC.PNG

Next up, we'll create a new schematic for the NMOS device with 4 pads connected to its 4 terminals.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post16.PNG

Going back to our layout for LVS check. It is crucial that you use the same terminal name for both layout and schematic or LVS will not work!

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post17.PNG


Our PMOS device layout connected to 4 pads in each of its terminal can be seen below.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post18.PNG

-Always making sure that you DRC your layout as you wire them up. When you're finished and DRC shows no error, you can go ahead and extract the layout.
-After the layout extraction, we'll create a new schematic for the PMOS device with 4 bond pads connected to its 4 terminals like below:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post19.PNG

-Going back to our layout window to LVS our files.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/trang/Lab4/post20.PNG

-LVS job completed and net-list match!!!!!


Saving My Work!!!

All files and images are backed up in a folder on my desktop,

I'll then send a copy to my email as a backup. 

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