Lab 6 - EE 421L 

Brandon Thomas (email:thomasb3@unlv.nevada.edu)

October 19, 2015

Objectives: In this lab we had to make the schematics for the NAND gate and the XOR gate using transistors as well as create their respective layouts.  After creating the gates, we then had to use these gates in an implementation of a full adder.  Once the schematic was created we also had to setup the layout for the full adder as well using the previously designed layouts for the NAND and XOR gates.  

Procedures: 

1) We had to start this lab off by completing Tutorial 4 in which we created the NAND gate.  The first thing we had to do was set up the schematic for the gate using NMOS and PMOS transistors.  A simulation was then done to test the NAND gate.  The following images were the results:

This was the setup used to test the NAND gate; only one of the inputs was changed while the other was held constant.

The following plot resulted when the input and output pins were probed.

We also had to create a symbol for the NAND gate that we could use when designing the full adder.

After setting the schematic up, the next step was to layout the gate, DRC the layout, then extract it and LVS check it.

2) After completing the tutorial, we then had to design an XOR gate.  The XOR gate had the same requirements as the NAND gate, the first of which was to set up the schematic and create a symbol for it.

Once the symbol was made, we had to use this symbol as well as the symbols we created for the NAND gate and the inverter from lab 5 in a single test circuit.

This schematic resulted in the following plots.

Then next step was then to layout the XOR gate, make sure it passes DRC, extract the layout, and make sure the LVS passes, just as in the case of the NAND gate.  The layout ended up looking pretty messy:

                                        Layout                                                                                            Extracted

   

3) Once we established that our gates were working correctly, we then had to use them to create the full adder.  The first task for creating the full adder was laying out the schematic.

We created a symbol for the full adder so that it could also be tested using the following schematic.

The full adder test schematic produced the following plot

4) After completing the stuff regarding the schematic of the full adder, we had to design the layout of the full adder, make sure it DRCs, then extract the layout, make srue it passes LVS.

Extracted

Conclusions:

The main that I learned from this lab and concluded from everything that the lab involved is that laying out something as simple as a full adder is way more complicated than I ever imagined.  The amount of wiring required was crazy, and became somewhat difficult to follow.  The hardest part for me was laying out the XOR gate.  Making sure all the terminals of all the transistors were laid out properly was very tedious.  However, it started to not look as daunting as it was originally when i finally got to laying out the full adder.  That was nowhere near as challenging but a few errors did arise when performing the LVS test.  The errors turned out to be due to things not being connected, which luckily didn't take too long to figure out.  It just showed me how careful you have to be when laying out these devices. 

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