Lab 2 - EE 421L 

Authored by Shada Sharif,

sharifs@unlv.nevada.edu

14 September 2015

Pre-lab work:

1. PART 1

• The zip file lab2 was downloaded and added to the desktop. A new directory called lab2 was created in the account, and in MobaXterm the file was unzipped to use the simulations provided.

• The ideal ADC and DAC sim schematic was opened as shown in the following picture

•  The simulation was then run. The spectre and cellview steps were added as a default setting in the .cdsinit as well as the background color was set to be white by default.
• To change either the line color or the line thickness we can double-click on the desired waveform and change the settings. This is shown in the next picture where the line was set to be solid with medium line thickness and the colors were changed as well.

2. PART 2
   

• An analog-to-digital converter works by taking in an analog signal like a sine wave and the output would be a digital signal (bits). The DAC works the same but in the opposite fashion. 
• Due to power supply of the circuit the output signal is limited, this means that since Vdd is 0V to 5V the output signal is only in this range so if we change the input signal Vin we see that the output clips at 0V and 5V due to its limitation from the Vdd as seen below.

• This is a 10 bit DAC/ADC circuit which means that the number of output levels that are possible corresponds to which is 1024 levels, and these levels would be from 0 to 5V. So to know the change per level in the 0~5V range we do , this can be seen in the picture below that the highest number the output wave reached was 4.99512V with is 4.88mV away from 5V. This is because the signal take at least 4.88mV to start which causes the output to not reach 5V exactly. If we wanted to have the output reach 5V we would use a higher bit DAC/ADC that gives smaller change per level.

3. PART 3

• In order to know the least significant bit from the ADC output or the DAC input we can plot the two extreme pins so either B0 or B9 and depending on the output we can tell which one is the LSB or the MSB. After plotting the pins output below we can see that B9 is high when the output is high which makes it the MSB and therefore B0 is the LSB. 

• Moreover the LSB could be known from the equation. This explains why the LSB plot seems to be changing because it takes at least 4.883mV from the input so that the ADC can consider 1 bit. 
• Lastly, explaining the concept of  how Vin is related to the B[9:0] pins and the Vout:
• The input signal is a sine wave which is analog, it goes through the ADC and then the output is discrete signals that are different on each pin depending on the pin the bit number it is.
• These individual discrete signal are then fed into the DAC and they are reformed to represent a sine wave, which we see in the waveform as stairs representing a sine wave. 
• This is all done internally by the DAC using resistor ladder, which will be used later in the post lab and explained in more depth.

• The signals above we have them arranged as Vout, Vin, and the from the MSB (net29) to the LSB (net37). 
• All the pre-lab work was backed up on dropbox

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Experiment #1

• The first part of the lab was to design our own DAC using 10k resistors. The design process will be shown in the following pictures:
• The first step was to make the resistor divider as the following using only 10k resistors, as well as naming the nodes
• Following this a symbol for the following schematic was made

• Using the symbol generated previously we start connecting the resistor ladder to make our DAC. The block generated above represents one bit so we connected 10 of them for the 10 bit DAC.
• Then a symbol for the R-2R was also made, we notice that at the end where we have the GndPin in B0 we added a resistor because we need to have 2R for the circuit.

• In creating the symbol for the DAC we went to the DAC schematic then used Create -> Cellview -> From Cellview. This was done instead of copying the ideal DAC symbol. We notice that the bits are in the upside down order thus when using the symbol we had to use bindkey r -> and rotate the symbol to the desired position.

• To determine the output resistance of the DAC we would need to ground all the input and combine resistances in parallel and in series as shown in the pictures below

• Now it is time to start testing the DAC we made in order to make sure it is operating correctly. The first test was to test the time delay of the DAC and to compare it to the hand calculations. So all the bit pins were grounded but B9 was connected to a pulse input as shown below, a 10pF capacitor was connected from output to ground, and the output waveform was generated. We are supposed to get an RC delay where R is the output resistance of the DAC and C is the capacitor we attached to the output.

• We see that the measured time delay from the waveform output matched the hand calculated delay. We first see that the output is half of the input due to the voltage divider so the Vout is around 2.5V and then we take 0.5*2.5=1.25V which is where we would measure the time delay. We got 77ns which is pretty close to 70ns calculated time delay.
• Two other tests were done with the DAC before attaching it to the ADC. One was attaching a resistor to the output, which should act as a resistor divider since the DAC has an overall output resistance of R so adding R of the same value on the output gives Vout=0.5*0.5Vin => 0.25Vin => 1.25V. The other test done was adding an RC to the output which is like the first test done with the capacitor alone but with a smaller overall all resistance. We would take 1.25*0.5=625mV and measure the time delay there with 0.7*R*C=0.7*5k*10pF=35ns.

 

 

• After testing that our DAC operates as expected, we now replace the ideal DAC with our DAC and test the operation of our ADC and DAC as well as compare to the prelab simulations.

 

 

• The convergence problem in the simulation was encountered, the simulation would only output up to 350ns, thus the instructions in lab were followed as shown in the picture above.
• We could see that the waveform we got is really similar to the prelab output, which means our design is working properly.
• Now we test the ADC_DAC with different loads:
• Resistor: similar to the simulations done previously in experiment #2, the resistor will act as a divider so we can see how to output wave is half of the input wave 0.5Vin=2.5V. Since we have an output resistance from the DAC and the added resistance to it divided the input.

•   Capacitor: we will get a delayed version of the input due to the RC effect of the capacitor and the overall output resistance of the DAC.

•   Capacitor & Resistor: the result to this load would be similar to the one previously done with a capacitor but with a smaller overall resistance of 5k instead of 10k due to having the output resistance of the DAC in parallel with the load resistor so 10k||10k=5k.

• In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). 
• Discuss what happens if the resistance of the switches isn't small compared to R.
• If the output resistance of ADC is larger than the resistance of the DAC input we could see loading effects that would cause the output voltage to be small. This would be mainly due to the voltage being mostly distributed across the higher resistance. We could also imagine this by having a large resistance in series with the 2R input of the bits and that will be in parallel with the 2R in the DAC so the overall resistance of the DAC would be larger. 

• backup was done again using DropBox

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