Project - EE 421L 

Authored by Emmanuel Sanchez,

Email: sanch512@unlv.nevada.edu

11/09/2015

Lab description:

For this final project, we will be fabricating chips using the C5 process through MOSIS. We begin by creating the schematics, simulations, and layouts of each circuit to ensure proper operation. Each chip will include the following test structures:

• Design of an 8-bit resettable (input "clear") up/down counter 
• The outputs of your counter should be buffered before connecting to a pad
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)     

Lab Report:

*PART 1 (Schematics and Simulations)*

Resettable 8-bit Up/Down Counter with Buffer

The first step towards creating the up/down counter is to build a D Flip Flop (DFF).

Schematic for DFF

Symbol for DFF

Schematic for 8-bit Up/Down Counter

Symbol for 8-bit Up/Down Counter

Schematic for Buffer

Symbol for Buffer

Schematic Used to Simulate Counter

Counting Up

Counting Down

Counting Up then Down

Using the Clear Signal

31 Stage Oscillator with Buffer  

Schematic for Oscillator

Simulating the 31-stage Oscillator:

Schematic for Simulating the Oscillator

Simulation Results

NAND and NOR Gates Using 6/0.6 NMOS and PMOS

Schematic of NAND Gate	Symbol for NAND Gate
Schematic of NOR Gate	Symbol for NOR Gate

Simulations for NAND and NOR Gates:

Schematic for Simulating NAND and NOR Gates

Simulation Results We can see that both gates function correctly for all possible inputs.

Inverter With Size 12/6

Schematic for Inverter

Symbol for Inverter

Simulating the Inverter:

Schematic for Simulating Inverter

Simulation Results - Transient and DC Sweep

Transistors: NMOS and PMOS measuring 6/0.6

Schematic for NMOS	Symbol for NMOS	NMOS connected to 4 pads
Schematic for PMOS	Symbol for PMOS	PMOS connected to 4 pads

Simulating the NMOS and PMOS:

Schematic for Simulating the NMOS	NMOS Simulation ID vs VDS
Schematic for Simulating the PMOS	PMOS Simulation ID vs VSD

25k n-well Resistor

Schematic for 25k Resistor	Symbol for 25k Resistor
Schematic for Simulating the 25k Resistor	Simulation Results - DC Sweep

Schematic for Voltage Divider	Symbol for Voltage Divider
Schematic for Simulating the Voltage Divider	Simulation Results - DC Sweep

DRC:

LVS:

DRC:

LVS:

DRC: In the following image, the first half of the layout is the oscillator and the second half is the buffer.

LVS:

DRC:

LVS:

DRC:

LVS:

DRC:

LVS:

DRC:

Zooming into the NMOS device:

LVS:

DRC:

Zooming into the PMOS device:

LVS:

DRC:

LVS:

DRC:

Layout:

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