Lab 5 - EE 421L
Authored
by Emmanuel Sanchez,
Email: sanch512@unlv.nevada.edu
9/28/2015
Lab
description:
Design, layout, and simulation of a CMOS inverter
Lab Report:
Layout and DRC of 12u/6u inverter:
-The body of the NMOS is connected to gnd! through a ptap and the body of the PMOS is connected to vdd! through an ntap.
-The input of the inverter is labeled "A" and the output "A_".
Extracted view of 12u/6u inverter:
Schematic and symbol of 12u/6u inverter:
LVS of 12u/6u inverter:
Layout and DRC of 48u/24u inverter:
-The body of the NMOS is connected to gnd! through a ptap and the body of the PMOS is connected to vdd! through an ntap.
-The input of the inverter is labeled "A" and the output "A_".
Extracted view of 48u/24u inverter:
Schematic and symbol for 48u/24u inverter (notice the multiplier is now 4):
 |  |
LVS of 48u/24u inverter:
Simulations:
The following schematic shows multiple 12u/6u inverters with different capacitive loads:
The following image shows the spectre simulation for the above schematic:
(Simulating 12u/6u inverter with loads of 100fF, 1pF, 10pF, and 100pF)
Comments:
-Capacitors take time to charge and discharge, and the higher the capacitance, the slower the voltage transitions will be.
-Here
we can see that the 100fF load does not affect the output
significantly, but as the capacitive load increases, the delay across
the inverter increases. The output of the 10pF load has just enough time to
transition between 0V and 5V, but the delay across the inverter loaded with 100pF is too
high and it does not allow the output to swing the entire 5V.
Repeating the simulation with the UltraSim simulator yields the following plot:
(The plots from this simulation are slightly less accurate than the ones from the spectre simulator but the difference is very small).
The following schematic shows multiple 48u/24u inverters with different capacitive loads:
The following image shows the spectre simulation for the above schematic:
(Simulating 48u/12u inverter with loads of 100fF, 1pF, 10pF, and 100pF)
Comments:
-Capacitors
take time to charge and discharge, and the higher the capacitance, the
higher the delay will be through the inverter.
-Here
we can see that the 100fF, 1pF, and 10pF all have enough time to
transition completely from 0V to vdd! and from vdd! back to 0V.
However, the 100pF capacitance is too high and the output
does not have enough time to swing from 0V to vdd! of from vdd! back to
0V.
-It
seems that larger inverters can drive higher capacitive loads than
smaller inverters. This makes sense because according to the equation C
= Q/V, more charge is required when driving a higher capacitance, and a larger inverter
has a larger area to provide that charge.
Repeating the simulation with the UltraSim simulator yields the following plot:
-The plots from this simulation are slightly less accurate than the ones from the spectre simulator but the difference is very small.
Here is a link to download my lab5 library and files:
lab5.zip
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