Lab 4 - EE 421L
IV characteristics and layout of NMOS and PMOS devices in ON's C5 process
Note: In all simulations for this lab, the body of all NMOS devices is connected to gnd! (ground) and the body of all PMOS devices is connected to vdd! (5V).
Lab Report:
Simulation #1: Simulating ID vs VDS of an NMOS device (W/L = 6um /0.6um) for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps.
Schematic & Simulation:
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Simulation #2: Simulating ID vs. VGS of an NMOS device (W/L = 6um /0.6um) for VDS = 100 mV wheree VGS varies from 0 to 2 V in 1 mV steps.
Schematic & Simulation:
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Simulation #3: Simulating ID vs. VSD of a PMOS device (W/L = 12um/0.6um) for VSG varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps.
Schematic & Simulation:
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Simulation #4: Simulating ID vs. VSG of a PMOS device (W/L = 12um/0.6um) for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps.
Schematic & Simulation:
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Making the Probe Pad:
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Layout of the NMOS connected to 4 probing pads (DRC no errors): 
Zooming into NMOS device and connections:
LVS of the NMOS connected to 4 probing pads (no errors):
PMOS with 4 Probe Pads
Layout of a 12um/0.6um PMOS device
Schematic and symbol of PMOS connected to 4 probing pads:
Layout of the PMOS connected to 4 probing pads (DRC no errors): 
Zooming into PMOS device and connections:
LVS of the PMOS connected to 4 probing pads (no errors):
