Lab 3 - EE 421L 

Authored by Emmanuel Sanchez,

Email: sanch512@unlv.nevada.edu

9/14/2015

Lab description:

The purpose of this lab is to layout and simulate a 10-bit Digital-to-Analog-Converter (DAC).

Lab Report:

Creating a 10k n-well resistor:

For the C5 process, the minimum width of the n-well is 3.6 um, or 12 lambda. To create the 10k resistor in this project, we use a width of 4.5 um beause it is greater than 3.6 um and also divisible by 0.15 um (to avoid grid errors). The sheet resistance per square is 800 ohms under the C5 process. This means we need 10,000/800 (=12.5) squares to create the 10k resistor. To find the length of the n-well, we multiply 4.5 um * 12.5 = 56 um. However, 56 um is not evenly divisible by .15 um (56/.15 = 373.333), so instead we use 56.1 um (56/.15 = 374).

The width and length of the reistor can be measured with the ruler (bindkey k).

After extracting the layout, we can see the actual value of the resistor turns out to be slightly higher than intented (10.21k).

     
The following image shows the schemactic of the R-2R blocks that will be used in the DAC schematic. The 20k resistor was implemented using two 10k resistors in series.

 
From the R-2R schematic, I created a symbol.

   
The layout for the R-2R block is seen below.

   
We can see in the extracted view that the n-well resistors are actually 10.21k and not exactly 10k as intended.

   
Using the symbol from the R-2R block, I built the schematic for the DAC.

 
Then I created a layout view in which I instantiated 10 R-2R blocks and connected them according to the schematic. The following image shows the layout with its DRC free of any errors.

 
Running the LVS confirms that there are no errors and the net-lists match.

   
After extracting the layout, I simulated the main schematic to confirm that everything still worked as expected.
The following two images show that the circuit is still functioning properly.

   

   
Here is a link to download my lab3 library & files:
 lab3.zip

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