Lab Project - EE421L 

Authored by Russ Prado,

prador@unlv.nevada.edu

11/9/2015

Lab Report:

First half of the Project:

• Design an 8-Bit resettable (input "clear") Up/Down Counter

Transmission Gates used in D-Flip Flop:25k-1k_Res_voltage-divider

 
D-Flip Flop with clearhttp://cmosedu.com/jbaker/courses/ee421L/f15/students/prador/

8-Bit Resettable UP/DOWN Counter:
Here I used a 2-1 MUX on each bit to control whether the counter will be counting up or down. When High is tied to the Up-Down terminal, it will count up, while a low input will allow for it to count down.

 
Simulations:

 
Up-Count:

 
Down Count:

 
Set:

 
Reset:

 
Set+Reset:

• 31-Stage Ring Oscillator with a buffer for driving a 20pF off-chop load

• NAND and NOR gates using 6u.6u NMOSs and PMOSs

• An Inverter made with a 6u/.6u NMOS and 12u/.6u PMOS

• Transistors, both PMOS and NMOS, measuring 6u/.6u where all 4 termainsl of each device are connected to bond pads 

• Using the 25k resistor laid out velow and a 10k resistor implement implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor)

• 8-Bit Resettable (input "clear") Up-Down Counter 

• D Flip-Flop with Set and Clear

• 31-Stage Ring Oscillator

• NAND Gate using 6/0.6 NMOSs and PMOSs

• NOR Gate using 6/0.6 NMOSs and PMOSs

• Inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS

• Transisitors: NMOS and PMOS, both measuring 6u/0.6u

• Voltage Divider using the 25k Resistor laid out below and a 10k Resistor

• 25k N-well Resistor

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