Lab 4 - EE421L 

Authored by Russ Prado,

9/21/2015

  

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process:

  

Prior to working on lab exercise, go through Tutorial 2.

 

Here, we will be generate 2 NMOS and 2 PMOS devices

Part 1:

Create the schematic ID v VDS of an NMOS device using the nmos symbol with an W/L ratio of 6u/600n


 

 Part 2:

Create the symbol of the schematic created in Part 1.

Part 3:

With this symbol, we will create and simulate the new schematic below:

 

  

  

  

 

Part 4:

Now, we will move on to a new layout cell called NMOS_IV_3. In this layout we will insert an NMOS device with a W/L ratio of 6u/0.6u. Don't for get to DRC the layout to make sure there are no errors. If there are no error, move on to extract the layout.

 


 
Part 5:
Now we will create the second NMOS device.
On this device we will simulate ID vs VGS when VDS=100mV and VGS varies from 0 to 2V in 1mV steps. This device will also have 6u/600n ratio.
 
Create the following schematic:

 
With the schematic built(don't forget to check save), simulate a DC analysis using ADE L. We will set the range for VGS

 
Part 6:
PMOS Device #1 (L/W=12u/600n)
For this PMOS Device, we will be creating a schematic to simulate ID v VSD using Parametric Analysis. VSG will be set from 0 to 5V in 1V steps, VSG will be set from 0 to 5V in 1mV steps.

The following are the schematic and simulation results:


 
Part 7:
PMOS Device #2 (L/W=12u/600n)
For this PMOS device, we will be creating a schematic and simulating for ID v VSG using DC Analysis. VSG ranges from 0 to 2 V in 1mV steps.


 
Part 8:
With all 4 of the devices built, we will now lay out a 6u/600n NMOS device and connect all 4 MOSFET terminals to probe pads.
We must make sure our layout passes DRCs as well as LVS it with a corresponding schematic.
 
Schematic and Layout:
 

DRC and LVS:


 
Part 9:
Lastly, we will lay out a 12u/600n PMOS device and connect all 4 MOSFET terminals to probe pads.
Like in Part 8, we must ensure out layout passes DRCs. Then LVS it with a corresponding schematic.
 
Schematic and Layout:

DRC and LVS:

 
Don't forget to back up your lab by compressing it and uploading it online.
 
 
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