Project - ECE 421L

Co Nguyen

11/8/2015

1st part:

Schematic of a 1bit counter with clock and clear

Schematic of a counter with clock and clear	Symbol of a counter with clock and clear

Simulation:

Schematic	Simulation

As we can see:

Clock	Clear	D	Q	Qi
Rising edge	1	1	1	0
Rising edge	1	0	0	1
x	0	x	0	1

Schematic of a 8-bit counter with clock, clear, and coutting up/down

Schematic	Symbol

Simulation:

Couting Down

Couting Up:

Couting Up/Down with reseting:

A 31-stage ring oscillator :

Schematic	Layout

31 stage ring oscillator and Buffer driving 20pF

Note: the oscillator won't to drive this big capacitor without buffer.

NAND and NOR gates using 6/0.6 NMOSs and PMOSs:

Gates	Schematic	Symbol
NAND
NOR		f

Gates	Schematic	Simulation
NAND
NOR

An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS:

Schematic	Symbol

Schematic	Simulation

Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad)

Simulation of NMOS and PMOS

Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) . To calculate Vout, we have Vout/Vin=R1/R1+R2, Vout= 285mV.

A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad) . Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit.

2nd part:

Layout NMOS and PMOS:

Layout Inverter:
Layout 1-bit counter

Layout ring oscilator:

Layout 8-Bit Counter:

Left side:

Right side:

Extracted:

Left side:

Right side:

LVS and Output (no error):