Lab 5 - ECE 421L 

Co Nguyen

9/28/2015 

  

Lab description: The purpose of this lab is to draft a schematic, layout, and symbol of an inverter

 Post lab:

Draft layouts, schematic, and symbol for two inverters having size of:

  1. 12u/6u (=width and length of PMOS and NMOS).
  2. 48u./24u where the devices use a multiplier, M=4(=width and length of PMOS and NMOS).
Devices12u/6u (=width and length of PMOS and NMOS).48u/24u (=width and length of PMOS and NMOS).
Schematicclick on imageclick on image
Layout-no errorclick on imageclick on image
Symbolclick on imageclick on image

Simulations:-using Spectre and UltraSim.

12u/6u Inverter schematic conneted to Vdd48u/24u Inverter schematic conneted to Vdd
click on imageclick on image

Inverters12u/6u -using spectre48u/24u -using spectre
100fFclick on imageclick on image
1pFclick on imageclick on image
10pFclick on imageclick on image
100pFclick on imageclick on image

When the capactior is small the response time for both is the same. However, the capactior is higher the respond time for 48u/24u is much more acurate and preceise than 12u/6u. We can see from the graph at 100pF of the 48u/24u has some inversion, but the 12u/6u does not invert and its output will become a constant number.

Set up UltraSim following: Setup->Simulator/Directory/Host and select UltraSim as seen below

click on image

Inverters12u/6u -using UltraSim48u/24u -using UlstraSim
100fFclick on imageclick on image
1pFclick on imageclick on image
10pFclick on imageclick on image
100pFclick on imageclick on image
 
The UltraSim and the Spectre give the same results as can be see from the graphs.When the capactor is small the respond time for both inverters are the same, but the capacitor is high the respond time of 48u./24u is more acurate than 12u/6u.

Saving my works to dropbox and email to myself:

click on image

click on image

Return EE 421L Labs