Lab 3 - ECE 421L
Prelab:
Continuing from the point in the tutorial where the circuit was simulated,
To draw: menu->create->shape->line
After drawing the lines:
(NOTE: If we had made the first cell as 'r_div', we will want to copy it
to a new cell called 'sim_r_div'. For reference, consider cell1 as
r_div, and 'cell2' as sim_r_div)
*Delete symbol in cell2
*Open schematic in cell2 and delete everything
Press 'i', browse to where cell1 is, choose symbol and place the new symbol in this schematic:
Check and save ....should only get 2 warnings (floating nets). If more, panic a bit, then fix whatever errors there. Re-check.
Once we have it down to these two warnings, we go to menu->check->find marker
On this window, hit 'ignore' twice (and untick 'show ignored' to not see them):
With circuit open, sim it: menu->ADE L -> load state (it exists,
but need to add outputs): menu->outputs->to be plotted->select
on schem
(select in, out...) menu->session->Save State
Green button (run sim), and the voltage division is reflected in the simulation result:
LAYOUT:
In cell1 hit menu->file->new->Cell View (if 'what's new' select menu->edit->off at startup)
NOTE: Type should be LAYOUT, not schematic!
[Layout window opens....looks a lot like schematic window]....look towards top left...hit 'AV' (all layers visible)
menu->view->redraw refreshes window
hit 'e' (display) tick box 'pin names shown', snap mode to 'diagonal'
Go to top left, click the 'n-well' in those colorful tabs on the left. Type 'r' for rectangle, draw it.
Type 'q' to edit properties. From the math, place the proper dimensions
in there (for left/right: -28, 28 and for down/up: -2.25, 2.25 , click
'ok')
Press 'f' to fit:
DRC it (menu->verify->DRC)
If all is right in the world, we'll have 4 errors:
Go to menu->verify->find marker 'zoom to markers' , 'ok'
It'll be a little off. After checking with ruler ('k') adjust so the left/right values are -28.05, 28.05.
DRC should have no errors.
Press 'i'. On left: NCSU_techlib_ami06 in middle: 'ntap', on right: 'layout'
On 2nd window (at the bottom...row of contacts should be 2, columns at 1)
Drag them on either side of the n-well
Press 'e' at bottom start 0 stop 10
'm', move them perfectly to each side of n-well, then go to menu->create->pin, and have metal1 selected at the left.
Draw the rectangle around part in the middle of both connectors, and name the left one 'L' and the right one 'R'
DRC it
Next, we'll add the res layer (the actual n-well resistance layer).
If you're a fellow student reading this part - you're lucky: There's a shortcut.
Just highlight the N-well in the middle:
Right click and select 'copy' , select 'change to layer', select
"res_id", then drag the whole thing back perfectly on top of itself.
Voila! You have a res layer on the n-well without having to draw all those squares:
DRC it - should be error free.
Save,
then go to verify->extract. Open extracted view and look at the
resistor value. Zoom in by one of the pins, and it should be near 10k:
Go to cell1, open its layout (if one isn't there - make it)
Hit 'i' and place however many n-wells in there as needed from cell2
DRC it....if errors, they're too close together....spread them out and try again.
To wire them, we now use metal layers...go to colorful tabs, hit
'metal1', hit 'r' and wire them together (if together)...or draw open
pins out to 'nothing' a bit (make a little blue square)
menu->create->pin
Do one for each named input/output (in, out, gnd! Exclamations are necessary for global)
Entire layout:
DRC it
Extract it *menu->verify->extract, 'ok'
Hit menu->verify->LVS....verify it against the schematic we drew
It should say 'success'. If not - panic.
We should see this:
and this:
Lab 3 DAC design using n-well resistors
Using the n-well configuration as outlined in the pre-lab, the DAC design will be implemented as per the LAB 3 assignment.
Using the circuit from Lab 2 to LVS against, we first create a folder, and start a new layout.
The, we place the resistors in vertical fashion along the y-axis:
For this configuration, there are 31 resistors in total, spaced ~18 lambda (no less) from one another.
Based off the actual schematic, we utilize the metal 1 layer to make the necessary connections.
For reference, here is the original diagram/schematic:
The metal layers connecting the resistors and pins are added.
To add pins, we select menu->create->pin. NOTE: The direction
(input, output, input/output) must correspond to the schematic.
The Layout is as follows:
(Lowest level: which is different from the other levels, as this 'block'
contains 4 resistors to correspond with the lowest resistor in the
schematic above gnd)
Also - the lowest pin is gnd!, and the upper pin is B0
The next levels (B1-B8) above this level are all similar, except the input pins are named differently to reflect the bit:
The top level (at B9) is different as there is the pin for Vout:
At this point, assuming the routing corresponds with the schematic, we can DRC it , then run an LVS to see if the two match:
The entire layout:
Verified (DRC)
The real joy was felt upon getting a successful LVS result:
Some items to be aware of:
Make sure that there no named nets where the resistors are connected
(other than the pins desired). Also, make sure that circuit is routed
correctly. Mine looked perfect, however upon closer inspection, I had to
re-route it for it to work properly.
Discussion Questions:
1) Discuss how to select the width and length of the resistor by referencing the process information from MOSIS:
The process information is available at MOSIS. Since MOSIS Scalable design rules require a 1/2 lambda grid for layouts, measurements scaled by lambda require would be halved with its negative and positive values reflecting length and width.
2) Discuss, in your lab
report, how the width and length of the resistor are measured:
R = R_square L/W
Min width: 12 lambda = 3.6um
If we made the width to be 4.5um, then
10k = 800(L/4.5um)
Solving for L we have:
L = 56.25 um
We then halve these width and length values to enter after creating the square and hitting 'q', and enter each value as negative (min), positive (max) respectively for width and height.
The .zip file for this lab is HERE
As for every lab, all work is backed up using my Dropbox account in an attempt to minimize the effects of Murphy's Law:
