Lab

Lab 2 - ECE 421L

Steven Leung

9/1/15

Prelab

Download lab2.zip to your desktop.

This archive contains a simulation example using an ideal 10-bit Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC).

Upload this zip file to the design directory on the server that you are running Cadence from, e.g., Tutorial_1, CMOSedu, etc.

Note that it's assumed you are using the NCSU Cadence Design Kits.

Unzip this directory and add, to your cds.lib in the design directory, the following statement (assuming the design directory is CMOSedu):

DEFINE lab2 $HOME/CMOSedu/lab2

Running the ideal ADC_DAC file with the loaded state yields the following plot

Questions:

2) An ADC takes a single analog signal and converts it to a digital signal (how every many bits the ADC is determines the resolution of the ADC). A DAC takes digital signals (multiple) and converts it to a single analog signal. One of the reasons why the output may not exactly replicate the input analog signal is becuase there is only 10 bits in the DAC, if there were maybe 10k the output will closely represent the input.

3) The LSB of a ADC would be the bit furthest away from the output on the resistor ladder. This can be figured out because when looking at a DAC, the bit furthest away from the output of the resistor ladder changing will cause the least change in output analog voltage.

The main purpose of this lab is to create a real DAC using a resistor ladder and then compare it to an ideal one. The DAC in the prelab uses voltage control voltage sources and therefore cannot be implemented on a chip.

We create our DAC by first creating a block for carrying one bit of the conversion. Therefore with this bit, we will be able to design a n bit DAC easily. The resistor value chosen for this design was 10K.

Since this labs requires a 10 bit DAC we combine 10 of the single bit (picture seen above) conversions. Each of the 10 squares seen below contain the single bit resistor circuit but as a symbol view as shown above.

Lastly, if we make the above circuit into a symbol view, we can easily see and simulate our 10 bit DAC. The picture below shows a simjulation with an ideal ADC driving our design for the DAC. This way we can cycle through most of the DAC input bits. This symbol can either be made by copying the Ideal_10-bit_DAC symbol from the library and drawing the 10 bit blocks in there or draw it in a new cell then click create ->cellview -> from cellview and assign pins corresponding to where you want them on the symbol.

Testing with my DAC Simulation result of my DAC

The output resistnace of our DAC can be calculated as shown below. From this we can see that the output resistance of the DAC depends on whatever value we choose for R.

To calcualte the delay of the the DAC while driving a 10pF load, we can ground bits 8-0 of the DAC and apply a step signal on bit 9. Since bit 9 is the MSB (most significant bit) , we should expect the output to go to VDD/2 when bit 9 goes to VDD. The delay estimation is given by .7*R*C where C is the output capacitiance and R is the output resistance (10K in this example). This value is calcualted to be 70 ns. To confirm this estimate, we can look at the graph and measure the time it takes the output to reach .25V (if Vin = 1V) since the final value of Vout is expected to be .5 volts (hence half of .5 is .25). The value measured on the graph is 1.07 us. The delay of the input is 1 us so if we subtract 1 us form the output, this gives us a delay of 70 ns which is the same as the estimated value from hand calcualtions.

The following pictures involve simulation my DAC with different types of load R,C,R/C

R=10K	C=10pF	R=10K and C=10p
Since the output resistance of the DAC is 10K when using a 10K load we can expect the output to be 50 percent of the input beucase of the voltage divider effect. The output resistance needs to be significantly less than 10K to be able to drive a 10K load.	We can see that with just a 10pF load, there is a phase change and the amplitdue is reduced by a little. Consider the output resistnace is 10K, this effect is becuase we now have an RC time constant causing the output to lag. The same concepts for RC circuits can be applied here with R= Rout and C=10pF. An important note here is that the staircase voltages on the output are not longer present. This is becuase voltage cannot change instantenouslly across a capacitor which causes the output to smooth out but at the cost of some delay time as seen above	If we combine the effect of having a 10K load with a 10pF load as seen from the results in the first 2 plots, this third plot is a result. The value for Rout is now 5K and C=10p. We can see that the magnitude is significantly reduced from both the voltage divider effect and the RC effect.

If the outputs switches of the ADC were implemented with transistors and the resistance of thsese swtiches were not small compared to R (10k) , a majority of the voltage drop will occur across the switches and as a result, the input of the DAC will see a very small voltage. This concept is similar to why when the DAC drives a 10k load, the signal is reduced by half. Ideally the resistance of the switch should be << R so that no loading effects occur.

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