Lab 7 - EE 421L 

Authored by Brian Kieatiwong

kieatiwo@unlv.nevada.edu

10/03/15

This lab consists of the creation of the schematic, symbol, and simulation of an 8-bit NAND gate, NOR gate, AND gate, inverter, OR gate, and 2-to-1 DEMUX/MUX. This lab will also show the schematic, symbol, and layout of an 8-bit full adder. This lab will have the cells available for download and show the backing up of all lab work.

The image above shows the simulation schematic of a 4-bit inverter using 6u/0.6u MOSFETs.

The image above shows the results of a 4-bit inverter using 6u/0.6u MOSFETs.

The image above shows the schematic of a NAND gate using 6u/0.6u MOSFETs.

The image above shows the schematic of an 8-bit NAND gate using 6u/0.6u MOSFETs.

The image above shows the simulation schematic of an 8-bit NAND gate using 6u/0.6u MOSFETs.

The image above shows the results of an 8-bit NAND gate using 6u/0.6u MOSFETs.

The image above shows the schematic of a NOR gate using 6u/0.6u MOSFETs.

The image above shows the schematic of an 8-bit NOR gate using 6u/0.6u MOSFETs.

The image above shows the simulation schematic of an 8-bit NOR gate using 6u/0.6u MOSFETs.

The image above shows the results of an 8-bit NOR gate using 6u/0.6u MOSFETs.

The image above shows the schematic of an AND gate using 6u/0.6u MOSFETs.

The image above shows the schematic of an 8-bit AND gate using 6u/0.6u MOSFETs.

The image above shows the simulation schematic of an 8-bit AND gate using 6u/0.6u MOSFETs.

The image above shows the results of an 8-bit AND gate using 6u/0.6u MOSFETs.

The image above shows the schematic of an inverter using 6u/0.6u MOSFETs.

The image above shows the simulation schematic of an 8-bit inverter using 6u/0.6u MOSFETs.

The image above shows the results of an 8-bit inverter using 6u/0.6u MOSFETs.

The image above shows the schematic of an 8-bit OR gate using 6u/0.6u MOSFETs.

The image above shows the simulation schematic of an 8-bit OR gate using 6u/0.6u MOSFETs.

The image above shows the results of an 8-bit OR gate using 6u/0.6u MOSFETs.

The image above shows the schematic of a 2-to-1 MUX gate using 6u/0.6u MOSFETs. This can also be used as a DEMUX by reversing the the input and outputs to be 1-to-2 DEMUX.

The image above shows the results of a 2-to-1 MUX gate using 6u/0.6u MOSFETs.

The image above shows the schematic of an 8-bit 2-to-1 MUX gate using 6u/0.6u MOSFETs.
 

The images above shows how Lab 7 work is to be zipped and emailed to myself for backup.

To download the cells from this lab, click here.

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