Lab 6 - EE 421L 

Authored by Brian Kieatiwong

kieatiwo@unlv.nevada.edu

10/19/15

This lab consists of the creation of the schematic, layout, and symbol of a NAND gate, XOR gate, and full adder. It will also show the simulation of all possible inputs for each respectively through SPICE. This lab will have the cells available for download and show the backing up of all lab work.

The image above shows the schematic of a 2-input NAND gate using 6u/0.6u MOSFETs.

The image above shows the layout of a 2-input NAND gate using 6u/0.6u MOSFETs.

The image above shows the extracted layout of a 2-input NAND gate using 6u/0.6u MOSFETs.

The image above shows the successful DRC of a 2-input NAND gate using 6u/0.6u MOSFETs.

The image above shows the successful LVS of a 2-input NAND gate using 6u/0.6u MOSFETs.

The image above shows the schematic of a 2-input XOR gate using 6u/0.6u MOSFETs.

The image above shows the layout of a 2-input XOR gate using 6u/0.6u MOSFETs.

The image above shows the extracted layout of a 2-input XOR gate using 6u/0.6u MOSFETs.

The image above shows the successful DRC of a 2-input XOR gate using 6u/0.6u MOSFETs.

The image above shows schematic for simulating the logical operation of the gates for all 4 possible inputs using Spectre.

The image above shows simulation parameters for simulating the logical operation of the gates for all 4 possible inputs using Spectre.

The image above shows the schematic of a full adder.

The image above shows the layout of a full adder.

The image above shows the extracted layout of a full adder.

The image above shows the successful DRC of a full adder.

The image above shows the schematic for simulating the operation of the full adder.

The image above shows the results for simulating the operation of the full adder.
 

The images above shows how Lab 6 work is to be zipped and emailed to myself for backup.

To download the cells from this lab, click here.

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