Lab 4 - EE 421L 

Authored by Brian Kieatiwong

kieatiwo@unlv.nevada.edu

09/28/15

This lab consists of the IV characteristics and layout of NMOS and PMOS devices. It will also show that the layout adheres to the DRC and LVS. This lab will also show the backing up of all lab work.

The image above shows the schematic of an NMOS device at 6u/600n for simulating ID vs VDS.

The image above shows the parameters VGS from 0V to 5V in 1V steps and VDS from 0V to 5V in 1mV steps.

The image above shows the simulation results.

The image above shows the schematic of an NMOS device at 6u/600n for simulating ID vs VGS.

The image above shows the parameters VGS from 0V to 2V in 1mV steps and VDS equivalent to 100mV steps.

The image above shows the simulation results.

The image above shows the schematic of a PMOS device at 12u/600n for simulating ID vs VSD.

The image above shows the parameters VSG from 0V to 5V in 1V steps and VDS from 0V to 5V in 1mV steps.

The image above shows the simulation resutls.

The image above shows the schematic of a PMOS device at 12u/600n for simulating ID vs VSG.

The image above shows the parameters VSG from 0V to 2V in 1mV steps and VSD equivalent to 100mV steps.

The image above shows the simulation results.

The image above shows the layout of an NMOS device connected  to 4 probe pads.

The image above shows the NMOS device at 6u/600n.

The image aboe shows the successful DRC.

The image above shows the successful LVS.

The image above shows the layout of a PMOS device connected to 4 probe pads.

The image above shows the PMOS at 12u/600n.

The image above shows the successful DRC.

 The image above shows the successful LVS.
 

The images above shows how Lab 4 work is to be zipped and emailed to myself for backup.

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