Project - ECE 421L 

Authored by Jesse Horsman,

11/9/2015

horsman@unlv.nevada.edu

  

Project - my end of semester project will be fabricated using the C5 process through MOSIS. This chip will be used next time EE 421L is taught to add an electrical measurement component to the lab.

First step is A 25k resistor implemented using the n-well:


Using the 25k resistor laid out below and a 10k resistor implement a voltage divider:


The Symbol:



And Sim:



Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
Nmos Circuit:

PMOS circuit:



And the transistor Circuit:



An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS







NAND and NOR gates using 6/0.6 NMOSs and PMOSs

    Nand Gate:

Nor Gate:

The Gate Circuit with sim:


A 31-stage ring oscillator:

Design of an 8-bit resettable (input "clear" and "load") up/down counter:

First the Latch:

The DFlipFlop:

Then the HardWare of the design:

Finnally the full circuit:

The simulation with up = 1 (aka 5V which means count up):

And the Simulation of the up = 0 (count down):

Now for the Layouts:

25K resistor:

The Voltage div:



Transistors:

Ring OSC:


NOR and NAND Gates:

The UP down counter:


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