Lab 6 - ECE 421L
This is the Layout of the XOR gate:
And this is the LVS of the XOR gate:
This is the test circuit for the inverter, NAND, and XOR gates:
The sim results of the test circuit above:
Using the above NAND and XOR gates, I have made a fulladder:
This is the LVS of the fulladder:
Having drawn out the skematic of the fulladder, I am able to test if for functionality:
This is the simulation results of all possibe inputs for the full adder:
