Lab 5 - ECE 421L
Authored
by Jesse Horsman,
10/5/2015
Lab
description:
- Draft schematics, layouts, and symbols for two inverters having sizes of:
- 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
- 48u/24u where the devices use a multiplier, M = 4 (set along with the width and length of the MOSFET)
12u/6u:
Circuit:
Simulation with 100fF:
Simulation with 1pF Capacitor
Simulation 10pF:
Simulation with 100pF:
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