Lab 2 - ECE 421L 

Authored by Jesse Horsman,

horsman@unlv.nevada.edu

9/14/2015

  

Lab description:

    Create a 10 Bit DAC and demostrate its usage

The Design of the 10-bit DAC (with 10k resistors)

How to determine the output resistance of the DAC (answer: R) by combining resistors in parallel and series:
     By working from the ground up (quite litterally) you can use the properties of parallel ressitances to break it down the the equilavent output resistance of 1 R.
   

Delay, driving a load:
    Since we determinded the output resistance to be 1 R, and given the capaitence to be 10pF,  
        .7*10k*10p = .7ns = Delay

    Verification:



Symble of the DAC:



Simulations of DAC



In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs).  
    What happens if the switches have a high resistance is that the balance of the circuit is thrown off, and that resistance would be componded by each bit, resulting in more increased output resistance and longer Delay.

How to create a symbol view for your design with the exact same footprint as the Ideal_10-bit_DAC symbol view:

   

Simulation of forced convergence:

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