Project I - EE 421L: Digital Integrated Circuit Design Laboratory

Octavio L. Gonzalez

gonzao1@unlv.nevada.edu

Lab description:

Generating a test chip layout for submission to MOSIS for fabrication.
 

Pre-Lab Scope

• Back-up all of your work from the lab and the course.
  
• Go through Cadence Tutorial 6.
  
• Read through the lab in its entirety before starting to work on it
• Form into groups of 4 students that will put the test structures on the chip.
  

Lab Work

• Design of an 8-bit presettable (input "Load") and resettable (input "clear") up/down counter
  
• The outputs of your counter should be buffered before connecting to a pad
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad)
  
• Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor)
  
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)  
  
• Whatever else you would like to fabricate to use the remaining pins on the chip
• In your CMOSedu.com lab account create a directory called lab8.
• Create a Cadence design directory called MOSIS_chipX where X is a number the lab instructor will assign after the groups are formed.

Post-Lab Scope

• Put the details of your chip (how to test it) in your lab report in this directory.
• Schematics with pin numbers and SIMPLE directions on how to test the chips should be the main content of these reports.
• Your report should include a link to your zipped up design directory for future reference.
  
• This design directory should be "clean" meaning that it only contains the cells (schematics, symbols, layouts, and simulations) used in the final chip.
  
• The top level cell, the one that will be fabricated, should be called topX and have both schematic and layout views so that it can be DRCed, and LVSed.
• Ensure that your html lab report includes your name, and the names of the other students in your group along with your email addresses at the beginning of the report (the top of the webpage).
  
• When finished backup your work (webpages and design directory).
  

Pre-Lab:

Below are the pre-lab deliverables.

Back-Up Work 

As can be seen, before starting, backing up all the work from the EE421 Lab and Course is required.

Lab 8 Review 

Below is a screenshot of reading through the Lab 8 requirements and scope prior to starting the assignment.

Tutorial 6

As can be seen below, Tutorial 6 has been completed.

Formation of Groups

The members that form this group are as follows:

Clinton Bess

Jimmy Malone

Jonathan Young

Octavio L. Gonzalez

Post-Lab:

Below are the post-lab deliverables.

Executable Chip Test Plan

The following are are the individual chip test structures and the detailed procedures to verify their operation

8-Bit Presettable/Resettable Up/Down Counter

Up Down Counter Symbol

Up Down Counter Schematic

Up Down Counter Simulation Schematic

Refer to miscellaneous section of this report for sub-level components and devices that make the 8-bit counter.

Simulation Reseting with Counting Up and Down

As can be seen above the clear input sets the counter to zero, after the signal is lifted the up count initiates then switches to down count accordingly.

Up Down Counter DRC

Up Down Counter LVS

31-Stage Ring Oscillator

Ring Oscillator Simulation Schematic

Refer to miscellaneous section for buffer design.

Ring Oscillator Simulation

With the output buffered, a 20pf load may be connected to the oscillator while retaining the square waveform.

Ring Oscillator DRC

Ring Oscillator LVS

6u/0.6u NMOS/PMOS NAND and NOR Gates

NAND and NOR Simulation Schematic

NAND and NOR Simulation

The simulation results for the mentioned gates are as expected based on the truth tables for the devices

NAND and NOR DRC

NAND and NOR LVS

6u/0.6u NMOS/PMOS Inverter

Inverter Simulation Schematic

Inverter Simulation

By sweeping the input to the gate the transfer curve above is generated, which agrees with a standard inverter profile.

Inverter DRC

Inverter LVS

6u/0.6u NMOS and PMOS Transistors

NMOS Transistor Simulation Schematic

NMOS Transistor Simulation

NMOS Transistor DRC

NMOS Transistor LVS

PMOS Transistor Simulation Schematic

PMOS Transistor Simulation

PMOS Transistor DRC

PMOS Transistor LVS

Voltage Divider - 25k/10k Resistors

Voltage Divider Simulation Schematic

Voltage Divider Simulation

Recall from the voltage division principle the output voltage agrees with the simulation.

Voltage Divider DRC

Voltage Divider LVS

25k n-well Resistor

25k Resistor Simulation Schematic

25k Resistor  Simulation

Recall from Ohms Law, the slope of the curve is the resistance and correlates to 25k Ohms.

25k Resistor DRC

25k Resistor LVS

10k n-well Resistor

10k Resistor Simulation Schematic

10k Resistor  Simulation

Recall from Ohms Law, the slope of the curve is the resistance and correlates to 10k Ohms.

10k Resistor DRC

10k Resistor LVS

Miscellaneous Devices

The following devices were sub-level components used for the main test structures.

D Flip-Flop

D Flip-Flop Schematic

D Flip-Flop Simulation

D Flip-Flop DRC

D Flip-Flop LVS

JK Flip-Flop

JK Flip-Flop DRC

JK Flip-Flop LVS

1-Bit Counter

1-Bit Counter Schematic

1-Bit Counter Symbol

1-Bit Counter DRC

1-Bit Counter LVS

Transmission Gate

TG Schematic

TG Symbol

TG DRC

TG LVS

Ring Oscillator

Ring Oscillator Schematic

Ring Oscillator Symbol

Buffer

Buffer Schematic

Buffer Symbol

Buffer DRC

Buffer LVS

Final Lab 8 Design Directory

The following is a link to the zipped chip design directory files for Lab 8

EE421 Lab 8 Design Directory.zip

Webpage and Design Directory Back-Up

The webpage and design directory was backed-up during the pre-lab portion of the lab.

Conclusion:

Lab 8 served as a means to generating a test chip layout for submission to MOSIS for fabrication using the ON's C5 process.

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