Lab 7 - EE 421L: Digital Integrated Circuit Design Laboratory

Octavio L. Gonzalez

gonzao1@unlv.nevada.edu

Lab description:

Using buses and arrays in the design of word inverters, muxes, and high-speed adders

Pre-Lab Scope

• Back-up all of your work from the lab and the course.
  
• Go through Cadence Tutorial 5.
  
• Read through the lab in its entirety before starting to work on it

Lab Work

• Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
• Create a 2-to-1 DEMUX/MUX schematic and symbol.
• Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
• Include an inverter in your design so the cell only needs one select input, S
• Finally, draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
  
• Create an adder symbol for this circuit (see the symbol used in lab6).
• Use this symbol to draft an 8-bit adder schematic and symbol

Post-Lab Scope

• Provide a few simulation examples using NAND, NOR, AND, inverter, and OR gates.
• Simulate the operation of a 2-to-1 DEMUX/MUX using Spectre and explain how it works.
  
• Make sure to show, using simulations, how the circuit can be used for both multiplexing and de-multiplexing.
• Use simulations to verify the operation of your 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
  
• Simulate the operation of your 8-bit adder.
• Lay out this 8-bit adder cell
• Show that your layout DRCs and LVSs correctly.
• For your lab report, use cell names that indicate the current semester and your initial
• Zip up these cells in a directory call lab5_rjb.zip (last two or three letters are your initials) and link to your lab report.
• As always ensure that your html lab report includes your name and email address at the beginning of the report (the top of the webpage).
• When finished backup your work (webpages and design directory).
  

Pre-Lab:

Below are the pre-lab deliverables.

Back-Up Work 

As can be seen, before starting, backing up all the work from the EE421 Lab and Course is required.

Saving the CMOSedu Directory Files to Folder EE421L Lab 7 BU 01NOV2015 on the Desktop

Emailing EE421L Lab 7 BU 01NOV2015 Zip to gonzao1@unlv.nevada.edu

Lab 7 Review 

Below is a screenshot of reading through the Lab 7 requirements and scope prior to starting the assignment.

Tutorial 5

As can be seen below, Tutorial 5 has been completed. Note: LVS and DRC without errors.

Post-Lab:

Below are the post-lab deliverables.

8-Bit Input/Output Gate Arrays

The following are a few simulation examples using NAND, NOR, AND, inverter, and OR gates.

Below is the 8-Bit NAND gate Schematic.

Below is the 8-Bit NAND gate Simulation.

Below is the 8-Bit NOR gate Schematic.

Below is the 8-Bit NOR gate Simulation.

Below is the 8-Bit AND gate Schematic.

Below is the 8-Bit AND gate Simulation.

Below is the 8-Bit OR gate Schematic.

Below is the 8-Bit OR gate Simulation.

2-to-1 MUX/DEMUX

The following is a simulation on the operation of a 2-to-1 DEMUX/MUX using Spectre as well as an explaination on how it works.

Below is the 2-Bit MUX Schematic.

Below is the 2-Bit MUX Simulation.

Below is the 2-Bit DEMUX Schematic.

Below is the 2-Bit DEMUX Simulation.

8-Bit Wide Word: 2-to-1 MUX

The following is a simulation of the 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol..

Below is the 8-Bit MUX Schematic.

Below is the 8-Bit MUX Simulation.

Below is the 8-Bit DEMUX Schematic.

Below is the 8-Bit DEMUX Simulation.

8-Bit Full-Adder

The following is the Full-Adder Schematic and Symbol

The following is theLayout and  Extracted Layout DRC/LVS Verifications for the Full-Adder

Webpage and Design Directory Back-Up

The webpage and design directory was backed-up during the pre-lab portion of the lab.

Conclusion:

Lab 7 served as a means to design, layout, and simulate a Full-Adder using the ON's C5 process.

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