Lab 5 - EE 421L: Digital Integrated Circuit Design Laboratory

Octavio L. Gonzalez

gonzao1@unlv.nevada.edu

Lab description:

Design, layout, and simulation of a CMOS inverter

Pre-Lab Scope

• Back-up all of your work from the lab and the course.
  
• Go through Tutorial3. 

Lab Work

• Draft schematics, layouts, and symbols for two inverters having sizes of:
• 12u/6u
  
• 48u/24u where the devices use a multiplier, M = 4

• Layout/Schematic Requirements:
• Your schematics should have two pins, e.g., A and Ai
• Your layouts should have 4 pins: A, Ai, vdd!, and gnd!
  

• Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load.

• Use UltraSim and repeat the above simulations.

Post-Lab Scope

• Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load.
• Comment, in your report, on the results

• Zip up these cells in a directory call lab5_rjb.zip (last two or three letters are your initials) and link to your lab report.

• As always ensure that your html lab report includes your name and email address at the beginning of the report (the top of the webpage).

• When finished backup your work (webpages and design directory).
  

Pre-Lab:

Below are the pre-lab deliverables.

Back-Up Work 

As can be seen, before starting, backing up all the work from the EE421 Lab and Course is required.

Saving the CMOSedu Directory Files to Folder EE421L Lab 5 BU 27SEP2015 on the Desktop

Emailing EE421L Lab 5 BU 27SEP2015 Zip to gonzao1@unlv.nevada.edu

Lab 5 Review 

Below is a screenshot of reading through the Lab 5 requirements and scope prior to starting the assignment.

Tutorial 3

As can be seen below, Tutorial 3 has been completed. Note: LVS without errors.

Post-Lab:

Below are the post-lab deliverables.

Extracted Layouts and Schematics

The following are the Extracted Layout and Schematic DRC/LVS Verifications

The following is the 12u/6u Inverter Device Symbol

The following is the 12u/6u Inverter Device Schematic

The following is the 12u/6u Inverter Device Layout with DRC Verification

The following is the 12u/6u Inverter Device Extracted Layout with LVS Verification

The following is the 48u/24u Inverter Device Symbol   

The following is the 48u/24u Inverter Device Schematic

The following is the 48u/24u Inverter Device Layout with DRC Verification

The following is the 48u/24u Inverter Device Extracted Layout with LVS Verification

SPICE Simulations

The following are the simulations for both the 12u/6u and 48u/24u inverters driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load.

Note: These simulations wer performed using the parametric analysis tool.

The following is the corresponding 12u/6u inverter device schematic..

The following is the corresponding 12u/6u inverter device simulation.

Note: As can be seen, with the larger capacitive loads, the RC time constant is also larger. The R is specific to the MOSFET W/L dimensions.

(UltraSim)

The following is the 48u/24u inverter device schematic.

The following is the corresponding 48u/24u inverter device simulation.

Note: As can be seen, with the larger capacitive loads, the RC time constant is also larger. The R is specific to the MOSFET W/L dimensions.

(UltraSim)

Note: Because the 48u/24u MOSFET has a smaller R than the 12u/6u MOSFET, the larger inverter is better suited for the larger capacitive load as the charge and discharce time constant is quicker than with the smaller dimension device.

Final Design Directory

The following is a link to the zipped design files and directory

Webpage and Design Directory Back-Up

The webpage and design directory was backed-up during the pre-lab portion of the lab.

Conclusion:

Lab 5 served as a means to design, layout, and simulate a CMOS inverter in the ON's C5 process.

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