Lab 4 - EE 421L: Digital Integrated Circuit Design Laboratory

Octavio L. Gonzalez

gonzao1@unlv.nevada.edu

Lab description:

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

Pre-Lab Scope

• Back-up all of your work from the lab and the course.
  
• Read through Lab 4 before starting it.
• Go through Tutorial 2. 

Lab Work

• Generate 4 schematics and simulations:
• A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.
• A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio. 
• A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio. 
• A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio. 
  

• Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small). 
• Show your layout passes DRCs. 
• Make a corresponding schematic so you can LVS your layout. 
• Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads. 
• Show your layout passes DRCs. 
• Make a corresponding schematic so you can LVS your layout.
  

Post-Lab Scope

• Document the Laboratory Excersise and Work.

Pre-Lab:

Below are the pre-lab deliverables.

Back-Up Work 

As can be seen, before starting, backing up all the work from the EE421 Lab and Course is required.

Saving the CMOSedu Directory Files to Folder EE421L Lab 4 BU 20SEP2015 on the Desktop

Emailing EE421L Lab 4 BU 27SEP2015 Zip to gonzao1@unlv.nevada.edu

Lab 4 Review 

Below is a screenshot of reading through the Lab 4 requirements and scope prior to starting the assignment.

Tutorial 2

As can be seen below, Tutorial 2 has been completed. Note: LVS without errors.

Post-Lab:

Below are the post-lab deliverables.

ID vs. VDS  Characteristics

The following is the schematic for simulating ID vs. VDS of an NMOS device for varying VGS.

ID vs. VGS  Characteristics

The following is the schematic for simulating ID vs. VGS of an NMOS device for varying VGS.

ID vs. VSD  Characteristics

The following is the schematic for simulating ID vs. VSD of a PMOS device for varying VSG.

ID vs. VSG  Characteristics

The following is the schematic for simulating ID vs. VSD of a PMOS device for varying VSG.

6u/0.6u NMOS Device Layout and Schematic

The following is a layout for the 6u/0.6u NMOS device connected to probe pads

The following is the NMOS Device Layout Symbol

The following is the NMOS Device Layout

The following is the NMOS Device Extracted Layout

The following is the NMOS Device Connected Pad Layout

The following is the NMOS Device Connected Pad Extracted Layout

The following is the NMOS Device Connected Pad Schematic

The following is the NMOS Device Schematic

The following is the NMOS Device Symbol

The following is verification that the NMOS Device Connected Pad Layout DRC's correctly

The following is verification that the NMOS Device Connected Pad Layout Simulation Schematic LVS's correctly

12u/0.6u PMOS Device Layout and Schematic

The following is a layout for the 12u/0.6u PMOS device connected to probe pads

The following is the PMOS Device Layout Symbol

The following is the PMOS Device Layout

The following is the PMOS Device Extracted Layout

The following is the PMOS Device Connected Pad Layout

The following is the PMOS Device Connected Pad Extracted Layout

The following is the PMOS Device Connected Pad Schematic

The following is the PMOS Device Schematic

The following is the PMOS Device Symbol

The following is verification that the PMOS Device Connected Pad Layout DRC's correctly

The following is verification that the PMOS Device Connected Pad Layout Simulation Schematic LVS's correctly

Conclusion:

Lab 4 served as a means to understand the IV characteristics and layouts of NMOS and PMOS devices in the ON's C5 process.

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