Lab 1 - EE 421L: Digital Integrated Circuit Design Laboratory
Laboratory introduction, generating/posting html lab reports, installing and using Cadence
Lab Work
Post-Lab Scope
Below are the pre-lab deliverables.
An email was sent to Dr. Baker at rjacobbaker@gmail.com requesting a CMOSedu account.
Reviewing material for editing webpages.
The
material for editing web pages was reviewed and used to construct this
html page.
Refer to image links and formatting for demonstion.
Post-Lab:
Below are the post-lab deliverables.
Tutorial Narrative
P2: The tutorial calls for a simple series DC circuit ,
to which the menues and bindkeys were used to construct the following schematic.
P3: With
the schematic complete, the simulation settings were configured to
transient analysis.
Furthermore, the waveforms to be plotted were selected as the "in" and "out" nodes.
P4: Finally
, after the simulation settings were defined, the waveform was able to
be plotted as shown below.
Note: Tutorial-1 continues on.
Back-Up Discussion
Back-Ups
will be performed regularly as suggested while working on the future
labs.
The method of choice will be .zipping the file and emailing to
gonzao@unlv.nevada.edu.
File name will be of the form: EE421L_Lab_N_BU NNXXXNNN. e.g. "EE421L Lab 1 BU 29AUG2015"
Lab 1 served an introduction to generating and posting html lab reports, as well as provided hand on training with installing and using the Cadence C5 Process.