Lab 7 - EE 421L

Using buses and arrays in the design of word inverters, muxes, and high-speed adders
Authored, by Clinton Bess
11/2/2015
Email: bessc2@unlv.nevada.edu

Postlab Deliverables:

Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates. Provide a few simulation examples using these gates.

AND Gate Simulation:



Above is an image of the AND gate symbol used in a simulation schematic. To its right is a simulation that corresponds with it. When both inputs contain a logic high, the the output also produces a logic high. Otherwise, a logic low is displayed in the output.


OR Gate Simulation:



Here is the a simulation schematic that uses an OR gate. When the either input receives a logic high, the output will also produce a logic high.


Inverter Simulation:



If a logic high signal is passed through in inverter the output result will be a logic low. If a logic low signal is passed an inveter the output result will be a logic high, hence the name inverter. Above is an image of the schematic used for the simlulation and the corresponding result.


NAND Gate Simulation:



Anytime one of the inputs in a NAND gate receives a logic low, the output will result in a logic high. Above are the simulations to show how this particular gate operates.


NOR Gate Simulation:



Whenever the input of a NOR gate is the same, the output will result in a logic high. Above is an example simulation.


Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.

Include an inverter in your design so the cell only needs one select input, S (the complement, Si, is generated using an inverter).



Above is an image of the modified MUX. Take note of the inverter that flips the input signal to the transmission gate.


Use simulations to verify the operation of your design.



Above is a schematic that is used for the simulation of the MUX/DEMUX. When the input signal 'S' receives a logic high, the value from the A input gets passed through the transmission gate to the output. If it the input signal is a logic low, the value from the B input gets passed through to the output.


Draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).



Here is the schematic of the full adder circuit. To the right is the corresponding layout.


Create an adder symbol for this circuit (see the symbol used in lab6). Use this symbol to draft an 8-bit adder schematic and symbol.



Above is an image of the schematic that was used to create the symbol. To the right is a layout that corresponds to the schematic.




Above are the neccessary DRC and LVS checks.




Here is an example simulation of the full adder. When a logic low and a logic high are added together, the result is a logic high in the output. When two logic high signals are added together the result is a logic low with a carry. This can be observed at the end of the second cycle.


As always... Backup your work!






Click the link below to download the Lab 7 files
Lab 7 Files