Lab 6 - EE 421L

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder
Authored, by Clinton Bess
10/19/2015
Email: bessc2@unlv.nevada.edu

Postlab Deliverables:

Draft the schematics of a 2-input NAND gate, and a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)

Create layout and symbol views for these gates showing that the cells DRC and LVS without errors

Use cell names that include your initials and the current year/semester, e.g. NAND_jb_f19 (if it were fall 2019)



Above is the image of the NAND gate schematic. To its right is the corresponding symbol.




The first image is of the layout of the NAND gate. Notice how it passes the DRC checks. The second image is of the extracted view of the layout. Notice how it passes the LVS checks.




The first image shows the schematic that was used to simulate the NAND gate. To the right is its corresponding simulation.




Above is the image of the XOR gate schematic. To its right, is the corresponding symbol.




The first image is of the layout of the XOR gate. Notice how it passes the DRC checks. The second image is of the extracted view of the layout. Notice how it passes the LVS checks.




The first image shows the schematic that was used to simulate the XOR gate. To the right is its corresponding simulation.


Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11)



The first image is of the schematic used to simulate the inverter, NAND gate, and the XOR gate. To the right are the simulation results. If you look closely you can small instances where the transient curve dips. These are caused by overlaps in the switching times. We can minimize these anomalies by applying proper logic minimalization techniques and precise calculations of the propagation delay.

Create a symbol for this full-adder



The first image shows the schematic of the full adder. To its right is the corresponding symbol.


Layout the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed

Full-adder inputs and outputs can be on metal2 but not metal3

DRC and LVS your full adder design




The first image is the layout for the full adder. I used a combination of metal 1 and metal 2 wires to create connections with the contacts. Notice how it passes the DRC checks. The second image is the result from extracting the layout. Again, notice how it passes the LVS checks.

Final Simulation



Above is the schematic used for simulating the final version of the full adder. To its right is the corresponding simulation.

As always... Backup your work!






Click the link below to download the Lab 6 files
Lab 6 Files