Lab 5 - EE 421L

Design, Layout, and Simulation of a CMOS Inverter
Authored, by Clinton Bess
10/5/2015
Email: bessc2@unlv.nevada.edu

Postlab Deliverables:

Draft schematics, layouts, and symbols for two inverters having sizes of:

12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)



The first image is the schematic of the inverter. The second image is the corresponding symbol.




The first image is of the layout of the inverter. Notice how it passes the DRC checks. The second image is of the extracted view of the layout. Notice how it passes the LVS check.


48u/24u where the devices use a multiplier, M = 4.



The first image is the schematic of the inverter. The second image is the corresponding symbol.




The first image is of the layout of the inverter. Notice how it passes the DRC check. The second image is of the extracted view of the layout. Notice how it passes the LVS check. Here Ai has to be connected to two paths of the metal 1.


Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load



Above is the schematic used for simulating the inverter(12u/6u). The results on the right are produced by using the parametric analysis tool in cadence. Essentially, I swept the capacitave load values from 100f F to 100p F by multiplying the previous value by 10 (100f, 1p, 10p, 100p). Notice how smaller values of the capacitance provide a shorter switching delay.

Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load



Above is the schematic used for simulating the inverter(48u/24u). The results on the right are produced by using the parametric analysis tool in cadence. Essentially, I swept the capacitave load values from 100f F to 100p F by multiplying the previous value by 10 (100f, 1p, 10p, 100p). Notice how smaller values of the capacitance provide a shorter switching delay.

Use UltraSim (Cadence's fast SPICE simulator for larger circuits at the cost of accuracy) and repeat the above simulations



The above images correspond to the simulations performed by using the UltraSim extension in cadence. The results are similar to those found in the previoius section except the lines in the curves are slightly more jagged. This can be attributed to the loss of accuracy UltraSim provides in order to produce a simulation in a smaller amount of time.



The above images correspond to the simulations performed by using the UltraSim extension in cadence. The results are similar to those found in the previoius section except the lines in the curves are slightly more jagged. This can be attributed to the loss of accuracy UltraSim provides in order to produce a simulation in a smaller amount of time.

As always... Backup your work!






Click the link below to download the Lab 5 files
Lab 5 Files