Lab 4 - EE 421L

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process
Authored, by Clinton Bess
9/28/2015
Email: bessc2@unlv.nevada.edu

Postlab Deliverables:

Generate 4 schematics and simulations.

A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.



The first image is a of the schematic used to simulate the current and voltage characteristics of the NMOS. The second image provides a parametric analysis in which VGS (gate-source voltage) is being swept from 0 - 5 V in 1 volt increments. Also VDS (drain-source voltage) is being swept from 0 to 5 V in 1 milli-volt increments.

A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.



The first image is a of the schematic used to simulate the current and voltage characteristics of the NMOS. The difference between this simulation and the previous one is the fact that VDS remains constant at 100 mV. In the second image, a transient anaylis is being performed on the provided circuit. Notice how the source and drain currents behave in a contradicting manner.

A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.



The first image is a of the schematic used to simulate the current and voltage characteristics of the PMOS. The second image provides a parametric analysis where VSG (source-gate voltage) is being swept from 0 to 5 volts in 1 volt increments. Also, VSD (source-drain voltage) is being swept from 0 - 5 V in 1 mV steps.

A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.



The first image is a of the schematic used to simulate the current and voltage characteristics of the PMOS. Here VSD remains constant at 100 mV while VSG is being swept from 0 to 2 volts in 1 mV increments. Similar to the NMOS, the drain and source currents are reflected about the x-axis.

Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small).

Show your layout passes DRCs.



The first image shows a zoomed view of the layout, focusing on the NMOS. The second image shows that the layout passed the DRC checks.

Make a corresponding schematic so you can LVS your layout.



The first image shows the schematic along with the pads that are connected. The second image shows the full layout and the completion of the LVS.

Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads.

Show your layout passes DRCs.



The first image shows a zoomed view of the layout, focusing on the PMOS. The second image shows that the layout passed the DRC checks.

Make a corresponding schematic so you can LVS your layout.



The first image shows the schematic along with the pads that are connected. The second image shows the full layout and the completion of the LVS.

As always... Backup your work!