Lab 3 - EE 421L 
Authored by Youssef Abdallah,
abdaly1@unlv.nevada.edu
September 21, 2015
   
Pre-Lab
       

• All worked backed up to Google Drive
• Finish Tutorial one. This was previously done in HW 4 

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 Lab Report
 

•  In this lab, a layout for the 10-bit DAC designed in lab 2 will be created.

  First, create a 10k resistor layout using n-well as discussed in Tutorial-1

•  The design of a resistor with a 10kΩ resistance in an n-well with a sheet resistance of 800Ω requires 10k/800 = 12.5 squares. Following MOSIS design rules with a λ of .3µm; a min well width of 12λ and well spacing of 18λ; a 12λ*0.3µm = 3.6µm width is required and a 12.5*3.6µm = 45µm length is required.
• The extracted view shows that the resistor is 10.24kΩ

 
  
 
Then, create a layout for the 2R-R schematic from lab 2 using the previous n-well 10k resistor
 

•  From  MOSIS SCMOS, these n-well resistors must  have a minimum spacing of 18λ; 0.3µm * 18 = 5.4µm. 

 
 

•  DRC was performed and it has zero errors, and LVS was run and the netlist matched for 2R-Rschmeatic and layout

 

 
Using the layout for the divider 2R-R, a new layout for the 10-bit DAC was created in my 10-bit DAC cell from lab2. Each layout was connected to its corresponding bit, B9 and Vout pin were connected to the first 2R-R layout, and B0 was connected to another n-well 10k resistor then to ground.
 

 
 

 

• A view of how each bit is connected to the following bit is showing in the following picture

 
 

• Again DRC has been performed for my_10-bit DAC layout and it is clean. LVS was run also and the netlist matches the schematic.

 
 
 

 
To make sure that the design works correctly, a simulation of my_ADC_DAC schematic was run with a 10k resistor and 10pF capacitor as load. The results are the same as the results from lab2 simulation
 
 
 

• The lab3 design directory could be downloaded from the following link lab3.zip

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 All the work has been saved and backed up to Google Drive
 

 
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