Lab 2 - EE 421L 
Authored by Youssef Abdallah,
abdaly1@unlv.nevada.edu
September 14, 2015
   
Pre-Lab
        Part 1:

• After backing up all the work to Google drive. Lab2.zip folder that contains the schematic for the ideal 10-bit ADC and DAC was downloaded as stated in the instruction. Then, it was extracted in CMOSedu directory to open the cell containing the circuit.

 

• Design of a 10-bit digital to analog converter (DAC)

• After loading the previous saved state in the downloaded folder; the following results were obtained after running the simulation 

 
        Part 2:

• An analog-to-digital converter is a device that converts analog or continuous signals into digital or discrete signals (digital representation), and its ideality is measured by the Resolution which indicates the number of discrete values it can produce over the range of analog values. 
• To better understand the circuit and how the output behaves, the offset of the input voltage was changed to 0V and from the following simulation it is concluded that the output has a limitation depending on VDD (which is from 0V to 5V). 

        Part 3:

• To determine the least significant bit, B9 and B0 (the extreme bits) are plotted with the input and output voltages, and by looking at the simulation it is clear that B0 is the LSB since it changes its value more frequently. B9 is the most significant bit. Also, LSB value = Vdd / (2^N)

 

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 Lab Report

        Part 1:
   
 To design a 10-bit DAC using an n-well R of 10k following the design topology given in the instructions, a schematic containing two 10k resistors is series with another one in parallel was created in a new cell called R-2R.
 


Then a symbol was created for this schematic to be used as a controlling input bit, with the input to the left, UP pin to connect to the previous bit and DOWN pin to connect to the following bit
 

 
Replacing each bit in the ideal DAC schematic with the new symbol, connecting all the terminal as following, a non-ideal DAC has been created. With the most significant bit connected to the output voltage and the least significant bit to ground
 

 
Finally, the ideal DAC has been replaced with a new symbol that corresponds to the new DAC created using n-well resistors in the Design of a 10-bit digital-to-analog converter (DAC) downloaded previously from lab2.zip folder
 

 
To verify that the design functions correctly a tran simulation was run, and results match the ideal design
 

 

 
        Part 2:
 
Calculate the time delay driving a capacitor of 10p F
Td = 0.7*R*C= 0.7*10p*10k = 70ns.  The simulation result matches the hand calculations as seen below
 
       
 

 

        Part 3:
 

• DAC driving a resistor load R = 10k ohm

 

 
 

   
        The simulation confirms the calculations
 

 

• If DAC drives a capacitor of 10p,F it will smoothen the output

 

 

 

• If the DAC drives a capacitor and a resistor in parallel. The output will decrease and look more like an analog signal

 
 

 

•  If the resistance of the switches connected to the DAC is not less than the value of R, The output voltage magnitude would decrease. It would be like a voltage divider.

 

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 All the work has been saved an backed up to Google Drive
 

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