Lab

Lab Project - ECE 421L

Ting Yu,

Email: yut2@unlv.nevada.edu

November 10, 2014

Lab description: Simulation and layout of an ALU with AND, OR, ADD, SUB

Part I: Design and Simulation of ALU

Following is the schematic of 8-bit ALU

Symbol for ALU.

F <0, 1>

00 A ADD B

01 A SUB B

10 A OR B

11 A AND B

Simulation

Simulation results

A AND B

at 25 ns

F0	F1	Operation	A0	A1	A2	A3	A4	A5	A6	A7	B0	B1	B2	B3	B4	B5	B6	B7	Z0	Z1	Z2	Z3	Z4	Z5	Z6	Z7	cout
0	0	AND	1	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	1	1	1	1	1	1	0

A OR B

at 125 ns

F0	F1	Operation	A0	A1	A2	A3	A4	A5	A6	A7	B0	B1	B2	B3	B4	B5	B6	B7	Z0	Z1	Z2	Z3	Z4	Z5	Z6	Z7	cout
0	1	OR	1	1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	1	0	1	1	0	0	0

A ADD B

at 165 ns

F0	F1	Operation	A0	A1	A2	A3	A4	A5	A6	A7	B0	B1	B2	B3	B4	B5	B6	B7	Z0	Z1	Z2	Z3	Z4	Z5	Z6	Z7	cout
0	0	ADD	1	1	0	1	0	1	1	1	1	1	1	1	1	1	1	1	0	1	0	1	0	1	1	1	1

A SUB B

at 255ns

F0	F1	Operation	A0	A1	A2	A3	A4	A5	A6	A7	B0	B1	B2	B3	B4	B5	B6	B7	Z0	Z1	Z2	Z3	Z4	Z5	Z6	Z7	cout
0	0	SUB	0	1	1	1	0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	0	1	0	0	0

Part II: Layout of the ALU

1bit ALU

Put eight 1bit ALU together to make 8bit ALU, connect all the ground and Vdd together. Connect F<1,0> together. Then connect the cout0 to cin 1. Cin 0 is connect to F<1>.

DRC and LVS for no error

back up all the files of the project.