Lab 3 - ECE 421L 

Ting Yu

Email: yu2@unlv.nevada.edu

9/27/2014

Lab description: Layout of 1 10-bit digital-to-analog converter (DAC)

Prelab: To layout the resistive divder

Start by creating a R_n_well_10k layout

Make a rectangle using the n_well layer for 10k resistor. With the sheet resistance of the n-well in C5 process about 800 ohms, the minimum width 12 lambda. Make the lenth 56.1 um by 4.5um.  Set the dimension of the rectangle like shown below.

Now add connection to the end of the resistor using NTAP (metal 1 connection to n-well). Set the columns to 2 to get two connecitons. 

It should look like the following.

Then add pins to the layout by adding metal 1 rectangle  and make sure to click the "Display Terminal Names" option. 

Now add the res_id layer, its the same size as the n_well. It should look like the following.

Then extract the layout. Go to Verify -> Extract. Open the extracted cell from library manager. Zoom in to see the resistor value. It should be close to 10k

Now we can draw the layout of R_div cell. Create a R_div layout view. Instantiate and add two 10k n-well resistor layout. Add metal 1 to connect resistors and Add pin name. It should look like the below.

DRC and LVS to ensure no errors. Then always remember to back up your files. 

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Main lab:  layout of 10-bit DAC that was designed and simulated in Lab2

1. How to select the length and width of the n-well resistor 

THe MOSIS Data sheet show the sheet resistance of the n-well in C5 process about 800 ohms/sq, the minimum width 12 lambda. Let's make the lenth 56.1 um by 4.5um.

2. How to measure the width and length by Electric

Press K or go to Tools -> Create Ruler. We can use this tool to measure the distance between length, width and between two contacts.

3. Degisn the DAC Layout

The minimum spacing between wells at different potential is 5.4 microns (18 lambda). Minimum wide of pactive is 2 microns. Minimum wide of n-well to pactive is 4.5 microns.I redesign the 2R_R as seen below and add a P+ ring to reduce noise. P+ ring is gound.

The following schematic is use for the 2R_R using three 10k n-well resistors plotted in Cadence.

Verify DRC and LVS to check for errors.

Next design the schematic of the DAC. Use the symbol from lab 2 and instantiate it create 10 of the it and link them together. Add ground, input pins, and output pins.

Top view

Bottom view

Next design the layout of 10-bit DAC. Instantiate the layer cell for the DAC bit into a new cell and make an array of 10 columns.Metal 1 use to connect up and down and gnd. Metal2 and via used to connect gnds together. 

Top view of the design.

Bottom view of the design.

Run DRC and LVS to check for no errors. 

Lastly, back up all the file of lab3 or found at this link.