Lab 2 - ECE 421L 

Ting Yu,

Email: yut2@unlv.nevada.edu

September 8, 2014

Lab description: Design of a 10-bit digital-to-analog converter (DAC)

Prelab: Simulation of 10-Bit ADC DAC

First download the lab2 zip file from this link

Then use MobaXTerm log into csimcluster.ee.unlv.edu

Upload the zip file into CMOSedu and unzip the file 

Add $HOME/CMOSedu/labl2  to the cds.lb file. Then Start Candance.

Find the lab2 Library and select sim_Ideal_ADC_DAC and open the schematic

The follow schematic of the ideal ADC DAC will shown like the following

Launch ADE. Then select Session -> load state -> cell view

Run the Simulation

At the rising edge of the clock Vout change and Vin value is sampled. 

The smallest possible change represents the LSB in the analog output voltage of the ADC. 10bit ADC is 2^10=1024. At 5V,  5V/1024=4.88mV.

POST Lab

In this lab we'll implement a 10-bit DAC useing 10K resistor based off the following design

Go to Cadance, make a copy of the sim_Ideal_ADA_DAC and Ideal_10-bit_DAC

 
In the Library manager go to file-> new-> cell view. Create a new cell view schematic call R2R look like the following.

Then go to create -> cell view -> from cell view, to create a symbol for this schematic.

Now open the copy of the 10-bit DAC and replace the schematic with the symbol we created. 

The symbol for this DAC will be updated since it was already created when we copy the file. open it and change the name. 

Now open the ADC_DAC circuit we copied and replace the ideal DAC with the one we created on the above. It will look like the following.
 

Simulations

Launch -> ADE L, make sure change the simulation option like below for it to work property. Go to simulations -> options -> Analog

Run transient analysis for 1us

With 10K resistor Load:

with added 10K resistive load the output signal become 2.5V. This is because the output resistance is 10K and by adding 10K load Vout is become half the Vin. Vin(R/(R+R))=Vin/2=Vout.

With a 10pF capacitor Load:

The 10pF capacitor smoothed out the Vout signal and shift the Vout signal out of the phase with Vin. (Time delay =0.7RC) Approximately 75ns time delay. 

With 10K resistor and 10 pF capacitor Load:

Vout is half the Vin and out of phase with Vin and the delay is abut 100ns.

Determine the output resistance of the DAC:
The resistor in the circuit can be combined in parallel and in series.
Combining 2R || 2R = R, R + R = 2R.
Repeat the process and the output resistance is Rout = R.

Delay, driving a load.
Ground all DAC inputs except B9. Connect B9 to a pulse source (0 to VDD) and show, and predict using 0.7RC, the delay the DAC has driving a 10 pF load
Hand calculation is 0.7RC = 0.7*(10k)*(10p)= 0.7ns 

The simulation result is about 75 ns which is close to estimated hand calculation.

In real circuit the swiches are implemented with transistors (MOSFETs), the output resistance of the DAC will increase if the resistance of the switches isn't small compared to R. The transistor parasitic resistance would cause the resistance to become larger and the output voltage would decrese.

Last let's back up!