Lab 7 - EE 421L 

Authored by Nha Tran

Email: trann4@unlv.nevada.edu

NHSE ID: 2000590233

10/27/2014 

Lab description: The objective of this lab is to create a schematic and symbol for an 8-bit input/output array for AND, OR, NAND, XOR, and Inverter gates. Using an array of buses on one symbol makes it look more concise and professional than having a column of buses connect to the same gate.

Next follow Tutorial_5 and it will show you how to connect buses and how to make a schematic and layout of a ring oscillator.

LAB:

 8-bit Inverter: first we instantiate the inverter from previous lab. then q it and change the Instance Name to IO<0:7> and set its Display to Value. Then finally we can add a thick wire by pressing shift+w and make some label like the schematic seen below.

Now we will connect different values capacitor to each bit to test if our 8-bit inverter works.

notice how each output is different this is because we have different cap values so we know that our 8-bit inverter works. when you increase the capacitor you also increase the rise time and fall time. When you use td=0.7RC to estimate time delay through an RC circuit. when you increase C td willl also increases. this is the same for rise time and fall time. we use tr=2.2RC

the rise time and fall time of an AND gate is affected the same way that the Inverter is.

8-bit NAND gate: the NAND gate was created in previous lab so all we have to do is connect it to a bus and make a symbol of that. 

now we sim it just like before with the AND gate and the Inverter. 

As was predicted the same thing happens for the NAND gate also when you increase the cap the rise time and fall time also increases. Since all the gates have to same time delay and rist time equation i will forego the simulation of the last 2 gates. 

8-bit NOR Gate: first we draft the schematic of a nor gate. And also make a symbol of it similar to below.

then we connect bus to like like we did in the previous gate. 

8-bit OR gate: similar to how we did the AND gate we will add an Inverter to the NOR gate to create the OR gate. 

Now we create the 8-bit OR gate the same way we did for the other 8-bit gates

8-bit 2-1 MUX/DEMUX: first we need to draft a schematic and symbol of a single 2-1 MUX, then we will add buses to it to make it a 8-bit.

   
next we need to create a circuit like below and sim it to see the function of the MUX

   
from looking at the graph below we see that when S=1 and Si=0 the output Z =A, and when S=0, Si=1 the output Z=B. this indicate that the MUX chooses either A or B depending on the value of S. So if S=1 it chooses A, if S-0 it chooses B.

We can consider a MUX as a multiple input single output switch, and a DEMUX is a single input multiple output switch. So for DEMUX we switch our MUX schematic by 180 degree then the input would be Z and the outputs would be A,B

8-bit 2to1 MUX/DEMUX: for our 8-bit 2to1 MUX/DEMUX we can place an inverter connected to the S and Si. and connect the rest of the pins to buses. Then we can make a symbol for it like below. 

Now create a circuit similar to below so we can sim our 8bit MUX

Now we create a Full-Adder as indicated on figure 12.20 on page 368 in CMOS book. first we will draft a 1-bit Full-Adder with its symbol.

now we sim it to see if it matches our Full-Adder from previous lab. and from closer inspection of the graph it does match the truth table below of a full adder. 

now we are ready to make the schematic and symbol for our 8-bit Full-Adder



Now we will sim this 8-bit full-adder to see if it function correctly. because An, Bn, Cn are all 2^8 so plotting everything would take up lots of space so i choose to let Cn=0 and just plot An and Bn with the output

   
the graph is hard to tell and there are some false output cause of the gate delay but if you count individual bits it does match the truth table.

lastly i will draft the layout of the 8-bit Full-Adder. 

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