Lab 8 - EE 421L
Braxon Tawatao
tawataob@unlv.nevada.edu
12-1-2014
Lab 8 Team Members (Team 5):
Cesar Macias
Stephen Berta
Braxon Tawatao
Chip design
For
this project our global ground will be pin (20) the number between the
parentheses denotes the pin number for the part being described.
Pmos: drain(7), body (6), source(5), gate(4)
Resitor 20k poly (37-38)
R 20k nwell (36-37)
Bandgap: VDD-bg(19), vref(18)
Inverter: vdd_inv(21), in(22), out(23)
NMOS: drain(15), gate(16), source(17)
Resistor 1k n+ (38-39)
Resistor 1K p+(39-40)
Charge pump: out(24), vdd(25)
ALU: cin(14), in1(13), in2(12), s<0>(11), s<1>(10), cout(9), out(8), vdd_alu(3)
61 stage ring oscillator: VDD_osc(28) osc-out(29)
Full chip project:
The files for this lab can be found here.
Backup of entire lab work for this semester:
Return to labs