Lab 3 - EE 421L

Braxon Tawatao

tawataob@unlv.nevada.edu

9/26/2014

Completing Tutorial 1 results in the following 10k n-well resistor:

 
And the extracted view showing a resistance of 10.21k:

 
The process information from MOSIS specifies that the sheet resistance of n-well is approximately 800 ohms per square.
Using this value, a 10k n-well resistor requires 10k/800 = 12.5 squares. The width of the resistor was chosen to be 4.5 microns or 15 lambda,
and therefore, the length of the resistor must be 56.1 microns or 187 lambda. This length was used both to make 12.5 squares and also to fit into the virtuoso layout grid.
 
Elements in a layout are measured in terms of standardized length called lambda. Lambda was mentioned earlier when discussing the length of an n-well resistor.
For this process, lambda = 0.3um = 0.3 microns.
 

 
Layout of the R-2R block from Lab 2:

 
Extracted view:

 
The extracted layout does LVS with the circuit schematic:

 
Laying out the DAC from Lab 2 using this R-2R component:

 
The completed layout of the DAC follows the design rules, and a DRC of the layout returns no errors:

 
Extracted view of the completed DAC layout:

 
LVS of the extracted layout versus the original DAC circuit schematic from Lab 2:

 
One final picture of the entire completed, extracted layout:

   
The full, zipped Lab 3 cadence design directory can be found here.
   
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