Lab 2 - EE 421L

Braxon Tawatao

tawataob@unlv.nevada.edu

9/12/2014

Pre lab:
For the pre lab, we were to simulate and experiment with the provided library of an ideal ADC and DAC.
Circuit schematic of ideal ADC/DAC:

 
Immediately simulating the operation of this circuit gave the following result.
The colors and graph asthetics of the sim result were changed from the default:

 
 The minimum analog voltage change that will cause a change in the least significant bit (LSB) of an ADC can be determined using the formula, VDD/(2^N),
where N is the number of bits used for the ADC's output. For this lab, N = 10.
Assuming VDD = 5V, this means that the voltage difference between binary numbers in this ADC is: 5/(2^10) = 5/1024 = 4.9mV.
For example, an input of 4.9mV should produce a '1' in the LSB of the ADC whereas an input of 9.8mV should produce a '0' in the LSB.
 
 
 

 
Initial Design: 
The first portion of Lab 2 was to design a 10-bit DAC using 10k resistor.
The DAC that was designed was based off of the topology given here.
To begin the design, I first created a building block consisting of 3 resistors with which to construct the DAC.
I created a symbol in the lab2 cadence library that represents these resistors as shown below.

 
Building this component in Cadence:

 
The final symbol:

 
 Using these resistor blocks I built a DAC based on the circuit shown earlier:
An extra 10k resistor (not shown) is also connected before Gnd.

 
And as was done with the resistor block, I created a symbol for my DAC:

 
Determining output resistance:
In order to calculate the output resistance, Rout, of the DAC topology shown above.
The resistors in that circuit can be combined in parallel and in series in an alternating pattern.
The resistors at the bottom of the circuit which are both connected to ground are in parallel and also both have resistances of 2R.
Combining them results in: 2R||2R = R. This equivalent resistance of R is now in series with the resistor above it which also has resistance R.
Combining: R + R = 2R. And now the process repeats. Thus, the output resistance of the DAC is: Rout = R.
The image below helps to illustrate this method and its result:

 
Delay driving a load:
 The delay for this DAC driving a 10pF load using 0.7RC where R = Rout = 10k is:
 0.7(1e4)(1e-11) = 7e-8 = 70ns
 
The following circuit was used to test how the DAC functions when driving various loads and was also used to confirm the delay calculations.

In the following simulations, the resistor and capacitor loads were kept or removed accordingly.
 
Capacitor Load:
The instructions specified to input the binary code B9 = 1, B8:0 = 0 (1000 0000).
This results in Vout being half of VDD or 2.5V. The rise time delay is about 75ns which is approximately close to the calculated value.

 
Resistor Load:
The simulation was run again with a resistive load of 10k. This is resistance is equal to that of the DAC's output resistance.
Thus, Vout driving the resistive load will be half of the expected value or 1.25V (the added load acts as a voltage divider).

 
RC Load:
 Combining the loads of the previous 2 simulations results in the following when the DAC drives this new RC load:
Vout in steady state is again 1.25V, but the delay is now roughly 40ns.
This change in delay arises from the fact that the DAC, the load capacitor, and the load resistor are all in parallel.
Calculating the new delay: 0.7(R_DAC||R_load)(10pF) = 0.7(10k||10k)(10pF) = 0.7(5k)(10pF) = 35ns which is half of the previous delay.
The simulation confirms this result:

 
Simulating my DAC in the original circuit:
 Substituting the MyDAC that I built into the sim_ideal_ADC_DAC circuit also using the symbol that was made for the MyDAC:

 
Simulating the operation of MyDAC with the original parameters:

  
This simulation originally had convergence problems, and the steps outlined in the lab instructions were followed:

 
Lastly, in a real circuit if the resistances of the MOSFET switches were not small compared to R,  the output resistance of the DAC
would be increased. The higher the number of digital inputs on the DAC the more the output resistance would increase. Essentially,
more input bits gives a greater resistance compared to the original output resistance of R.

Lab 2 is backed-up:

 
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