Lab 6 - ECE 421L 

Authored by Silvestre Solano,

Email: Solanos3@unlv.nevada.edu

Schematics of the 2-input NAND and XOR gates

The design of the 2-input NAND and XOR gates is fairly simple since professor Baker pretty much did the whole thing for you. Although I could have easily copied the files he gave us to save time, I decided to build everything from scratch. For the NAND gate, I instatiated two PMOS and two NMOS, and set them to have a W/L of 6u/0.6u. I connected them together according to the schematic in the lab webpage and added the A and B input pins and the output pin ANANDB. The final schematic is shown below.

From the above schematic, I created a symbol view as shown below.

This of course looks nothing like the typical NAND gate Symbol. So, the above symbol was redrawn to be more like its well known symbol. The final result is shown below, with my initials shown in the middle of the NAND gate.

The above concludes the drafting of the NAND gate. Now, I move on to the schematic of the XOR gate. Clearly, this design is a bit more complicated than the NAND gate. Luckily, professor Baker was kind enough to provde the schematic for this XOR gate. To begin, I instatiated 6 PMOS and 6 NMOS both with the W/L of 6u/0.6u. I then connected them according to the provided schematic. And as always, I added the correct input and output pins, which are the same as the NAND gates. Also, wire labels were added. The final schematic for the XOR is shown below.

Next, from the above schematic, the symbol below is created.

As before with the NAND gate, the XOR symbol has to be redrawn with my initials in the middle. The final result is as follows.

Simulation of the NAND and XOR gates.

The simulation for both gates is also quite simple because professor Baker also gave us the schematic and expected simulation results. However, I do not understand why he used the inverter in the schematic for the simulation. But I assume the inverter is there for a good reason, so I used it as well. I used the 12u/6u inverter I created in Lab 5. I also instatiated the NAND and XOR gates. This is shown below.

Next, I connected them according to professor Baker's simulation schematic as shown below. 

The parameters for the pulse sources are shown below

For the simulation to work, I had to add the PMOS and NMOS models to the simulation parameters as shown in the following picture.

The final simulation parameters are as follows.

And finally, the simulation results, which test every possible two-input combination (00, 01, 10, and 11), are as shown below. In the below simulation, there is a "spike" for the output of the XOR gate at the 200 ns mark. This is due to the simultaneous change of both A and B. At a certain point in that time interval, the A and B outputs appear to be identical, which cause the output of the XOR gate to spike to zero at the 200 ns mark. This is of course a glitch, because at that transition, we expect the XOR gate to stay at a steady state of 5 volts between 100 ns and 300 ns.

Layout of the NAND and XOR gates.

As before, the layout of the NAND gate is quite easy because it was already done for you in Tutorial 4. So to begin, I instatiated two NMOS and two PMOS and set their W/L to 6u/0.6u. Then I "merged" the NMOS and the PMOS which resulted in the following. 

After making all the appropriate connections and created the correct pins to match the schmatic, I DRCd it to check for errors. There were no errors and the final layout along with the command interpreter window that shows that there were no errors is shown below.

Next, the layout was extraced and the result is shown below.

Then I used the LVS in order to compare it to the schematic. It worked and the results are shown below.

And then there is the XOR layout. This time professor Baker did not supply us with the layout so I had to design the whole thing myself.

To begin, I instatiated 6 PMOS and 6 NMOS with the same W/L as used for all the previous schematics and layouts. This is shown below.

4 PMOS and 4 NMOS were merged together as shown below.

After 3 hours of work, I had finally connected everything in the right place and added the correct pins. I DRCd the layout with no errors and then extracted it. Then I used LVS to compare it to the schematic. The LVS ran successfully but the net lists did not match. In order for the net lists to match, I had to add the inputouput pins labeled Ai and Bi in the schematic as shown below.

Then the LVS ran correctly. The below picture shows the complete layout with the CIW showing no errors in the DRC.

The extracted layout is shown below.

And finally, the successfull LVS is shown below.

Schematic and simulation of the full adder.

The schematic for the full adder was again provided by professor Baker. I used his schematic to build my own by instatiating 3 NAND gates and 2 XOR gates. Connecting them together and adding the appropriate pins results in the following schematic.

A symbol is created for the full adder and is shown below.

The circuit for the simulation is constructed using 3 pulse sources and the correct input and output pins were created. The completed schematic is shown below.

The simulation parameters for the pulse sources is shown below

 a                                      b                                      cin

The simulaiton parameters are as follows. This of course includes the PMOS and NMOS library models.

The simulation was designed to test every possible input combination of a, b, and cin according to the following table.

And last but not least, the simulation results for the full adder are shown below.

As before, the "spikes" that appear in the above simulation are caused by the simultaneous transition of pulse signals, giving the wrong input combination for an extremely short period of time. The above simulation shows two spikes in the output of the s bit. 

Layout of the full adder

The layout of the full adder is were the real fun begins. To start this arduous task, I instatiated 3 NAND gates and 2 XOR gates in their layout forms. In order to modify them for the full adder, I had to flatten them as shown below.

Then I stretched the NAND gates so that their height was the same as that of the larger XOR gate as shown below.

I deleted the individual vdd and gnd so I could merge them togetehr. Then I put the gates as close as I possibly could as the following picture shows.

An hour later and I had the follwoing layout.
 

 
It is at this time that I notice that the output cout was all the way on the left. I realized that the layout design might be better if the cout was all the way on the right were I could easily attach other things to it in the future. So, I had to move the leftmost NAND gate and rearrange some connections.
 
After 4 hours, I finally ended up with a layout that I thought was flawless. Notice that I designed the layout so that the inputs are on the left so they can be accessed easily for future projects. The outputs are all the way on the right for easy access. This layout is shown below.
 

I noticed that the above layout did not have the vdd! and gnd! pins, so I added them. I did the standard procedure and DRCd it with no errors, then I extracted it. Then I used LVS, which unfortunately for me, came out showing that the net lists did not match. So I spent another good hour or so trying to figure out what was wrong. The LVS error is shown below.

The error "Net /13 merged with /24" means that some connection is missing in the layout that is present in the schematic. After some minutes of searching the schematic, I found the connection missing, which is highlighted in the picture shown below.

So, I went to the layout and made the missing connection as shown below.

Finally. After spending my Friday and Saturday working on this monstrosity, the complete and correct layout for the full adder is shown below.

I DRCd the above layout and found no errors. This is shown below.

The above layout was extracted as shown below.

And finally, the net list matched on the LVS as shown in the picture below.

The following two pictures show a close up of the input and output pins.

This concludes this extremely time consuming lab.

As always, I will back up my work on my laptop and flash drive as shown.

My completed Lab 6 directory can be obtained from this zip.

Return to the main Lab directory.