Lab 5 - ECE 421L 

Authored by Silvestre Solano,

Email: Solanos3@unlv.nevada.edu

Schematic of inverter with W=12u/6u (width of PMOS/NMOS) and L=0.6u

To begin the lab, a PMOS and an NMOS must be instatiated into the schematic. The width of the PMOS will be set to 12u and the width of the NMOS will be set to 6u. Both devices will have a lenght of 0.6u. The PMOSwill b e placed on top of the NMOS. Both of their gates will be connected together and will have an input pin called "A." The drains of both devices will also be linked to together with the ouput pin "Ai." The source of the PMOS will be set to vdd and the source of the NMOS will be set to ground (gnd). This essentialy forms the 12u/6u inverter and the complete schematic is shown as follows.

The symbol view of the schematic is created from the schematic view and is saved as a new file within the cellview,
 

 
The following symbol appears.
 

 
The symbol shown above does not look like the well known symbol of an inverter. So it was edited to appear like the symbol of an inverter, which is just a triangle with a circle on it, as shown below.
 

 
 

The layout of the inverter follows similar steps as the schematic. The first step in this layout is to instatiate the PMOS and the NMOS. The PMOS is always on top of the NMOS in this layout.
 

 
The width of the PMOS is set to 12u and the length is set to 0.6u.
 

 
The NMOS is set to have a width of 6u and a length of 0.6u.
 

 
As before, the gates of both devices are connected together with a pin called "A."
 

 
The rest of the layout is relatively simple. Both drains of the devices must be attached together with a pin called "Ai." The source of the PMOS will be attached to vdd using an ntap with a row of four contacts. The source of the NMOS will be attached to ground (gnd) using a ptap with a single row of three contacts. In the layout, there is an exclamation mark after the vdd and gnd to indicate that they are global values. The completed layout, showing that the DRC check was completed successfully with no errors, is shown below.
 

 
After the DRC passed successfully, the layout was extracted.
 

 
The LVS command was ran to compare the extracted layout and the schematic built in the first part. Much to my great misfortune, the LVS did not run successfully.
 

 
As always, this failure was a result of some dumb check and save thing. After checking and saving the schematic, the LVS ran successfully without any errors with a matching net-list.
 

 
 

The schematic, symbol, and layout of the 48u/24u inverter is nearly identical to the 12u/6u inverter previously done. So, I will skip some of the explanation in the following picutres since the procedure is essentially the same as previously discussed. For the schematic portion of the 48u/24u inverter, the schematic of the 12u/6u inverter was copied and the multiplier was set to 4. The completed schematic is shown below. Note the m=4.
 

 
 

 
 
The symbol is shown below.
 

 
 

A PMOS and an NMOS are instatiated and the PMOS, which has the same dimensions already set from the previous layout, has its multiplier set to 4.
 

 
The NMOS, which has also retained its dimensions from the previous layout, also has its multiplier set to 4.
 

 
Their gates and drains are connected together with the same pins as the previous layout. The vdd and gnd connections are done in the same manner as in the previous layer, with a different number of contacts for both vdd and gnd. The completed layout is shown below with the command interpreter window showing no errors for the DRC.
 

 
The extracted layout is shown below.
 

 
Using the LVS command to compare the extracted view shown above and the schematic shows that the net-lists match, which of course implies that the LVS itself completed successfully.
 

 
 
 
Simulation of 12u/6u inverter using a 100fF, 1pF, 10pF, and 100pF load capacitor (Spectre).
 
 
In order to simulate the inverter, an appropriate schematic is built by first instatiating the 12u/6u inverter from the Lab_5 directory in the library.
 

 
Then, a 5V vdd, a pulse source that jumps from 0 to 5V, and a 100fF capacitor are added as shown below.
 

 
In order for this simulation to actually work, models of the NMOS and PMOS must be added to the ADE L as shown below.
 

 
The paramaters of the pulse voltage source are shown below.
 

 
And last, but not least, the complete ADE L simulation parameters are shown below.
 

 
This simulation will be done four times for each different value of the capacitor. This means that the circuit will have its capacitor changed for each simulation. The following four pictures illustrate the individual simulation results.
 
100fF

 
1pF

10pF

100pF

From the four above simulations, it is easy to see that as the capacitance becomes bigger, the capacitor need more time to fully discharge and match the inverse of the input pulse. When it was only 100fF, the capacitor was able to discharge and charge fast enough to keep up with the pulse source. However, at larger values, such as 1pF, the capacitor required more time than what was given in order to charge and recharge. Thus, the output from the capacitor almost looks like a straight line in the picture directly above this paragraph. 

Simulation of 12u/6u inverter using a 100fF, 1pF, 10pF, and 100pF load capacitor (Ultrasim).
 
This part is identical to the steps done previously with the Spectre simulations.
 
To begin, the ADE L is set to run using Ultrasim.
 

 
The models of the PMOS and NMOS must be added.
 

 
The following are the four simulations for the different values of the capacitor, which was done in the same manner as the previous simulations in Spectre.
 
100fF

 
1pF

 
10pF

 
100pF

 
The simulations appear to be exeactly the same as the ones done in Spectre.
 
 
 

The following steps to create the simulaions for the 48u/24u inverter are the same as the ones done before for the 12u/6u inverter, so I will skip some of the explanations. For the 48u/24u inverter, the schematic for simulation is shown below. This schematic is the same as the one before except the 12u/6u inverter is deleted and replaced by the 48u/24u inverter.
 

 
The ADE L simulation parameters for Spectre are shown below.
 

 
The four simulation results are as follows,
 
100fF

 
1pF

 
10pF

 
100pF

 
The simulation results above have essentially the same explanation as the simulations for the 12u/6u inverters. However, since the 48u/12u inverter is four times bigger dimensions than the 12u/6u inverter, the signal has to go through a smaller resistance, which gives it more time to discharge and recharge than the 12u/6u inverter. This is best illustrated in the simulations for the 100pF capacitor for both the 48u/24u and the 12u/6u inverters. In the 12u/6u inverter, the width is smaller, therefore there is a larger resistance of the PMOS/NMOS, which leads to a slower charge and discharge. However, the 48u/24u inverter has a larger width, which creates a smaller resistance that allows the capacitor to charge and discharge faster. This is easily seen by comparing the pictures for both 100pF simulations. In the case of the 12u/6u inverter, the charge and discharge of the capacitor almost looks like a straight line (left) and for the 48u/24u inverter, the charge and discharge does not look as straight (right).
  

 

Again, this is identical to the Ultrasim simulations done before for the 12u/6u inverter. First the Ultrasim simulator must be selected in the ADE L.
 

 
The complete simulation parameters are seen below.
 

 
The four simulations are as follows.
 
100fF

 
1pF

 
10pF

 
100pF

 
These simulations are identical to the previous ones. This concludes lab 5.
 
 
 
As always, backups are made as shown below.
 

 
 
The files used for this lab are found here. Note that there is only one schematic for each of the inverters used. In order to use different values of the capacitor for each, one must manually change the capacitor. In other words, there are only two simulating schematics and not eight.
 

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