Lab Project - EE 421L 

Authored by Brian Smith (smith945@unlv.nevada.edu),

November 10th, 2014

  

This project is to design an ALU that will perform addition, subtraction, AND and OR operations on two eight bit signals. 

 

Part 1:
The first part of the project is to create the schematics and symbols for the adder. It should have three inputs, A(8-bit), B(8-bit) and F(2-bit). It should also have one output Z(8-bit). A and B are the signals that are added, subtracted, AND'd and OR'd. F selects the operation to perform. Z is the output.
 
Firstly, I will summarize the schematics for the gates made for the last few labs that will be used in this project. Firstly, there is a simple inverter and an 8-bit wide version.
 
Then there is an AND gate, which is a NAND gate with an inverter on the output.
 
Then the or gate, which is a NOR gate with an inverter on the output.
 
Then there is the full adder. The 8-bit full adder schematic is unlike the other 8-bit gates, in that the 8-gates are tied together Cout to Cin, with the Cin and Cout of the 8-bit gate being the Cin of the first gate and the Cout of the last gate, respectively.
 
The multiplexer, takes two signals and outputs only one of them, determined by a select input and its complement. The 8-bit version has the select complement being generated by an inverter for convenience.
 
With the components made, now the ALU can be designed. The ALU to be designed needs to be able to and, or, add, and subtract two 8-bit signals. To do this, I first make the adder-subtracter. I used one 8-bit full adder to do this. I had the A signal go directly to it. The other input came from a multiplexer that selects B for addition and an inverted B for subtraction. The inputs to the multiplexer are chosen so that selecting the inverted B signal also sends a 1 to the carry in of the adder (to make the inverted B signal 2's complement), and a 0 to the carry in to not interfere with the addition.
 
Then the A and B signals are sent to the AND and OR gates, combined with a multiplexer using the same select signal as the adder-subtracter. The output from these two groupings is then selected between by a final multiplexer. The selector signals are then combined to be the 2-bits of the F signal input. The most significant bit of the F signal is chosen arbitrarily chosen for the first bit to be the selector for the adder-subtracter/and-or and the second bit being the output selector. This makes F(00)=ADD, F(01)=AND, F(10)=Subtraction and F(11)=OR.
 
The resulting schematic is shown below.

 

With that, the ALU has been designed. I then made a symbol for this ALU.

 

Then, I made a schematic to simulate it. The test inputs are A=35=0b00100011 and B=22=0b00010110, with F being driven by pulses so that all the combinations of F's bits are generated.

 

This was then simulated. Here are the settings.

 

And here is the output.

 

To make sure that the output is correct, I calculated what I should get.

The inputs are:

A=35=0b00100011

B=22=0b00010110

 

So I should get:

35 + 22 = 57 = 0b00111001

35 AND 22 = 0b00000010

35 - 22 = 13 = 0b00001101

35 OR 22 = 0b00110111

 

As can be seen in the output simulation, this is the result that I got, so the ALU is working correctly.

 

My library backup for part 1 is located here.

  

Part 2:

 

 The second part of the project is to layout the full ALU. In order to make the layout easier, I first made layouts of the individual components. First up is the inverter.

 

 

 This passes a DRC and a LVS.


 

 

I then used that cell to make the 8-bit version.

 

 

This passed a DRC, as shown below.

 

 

  After extracting the inverter layout, I ran a LVS, showing that they layout and schematic match.

 

 

Now for the AND gate layout, I followed the same process. First the individual and gate was made, DRC'd and LVS'd.

 

 

 This passes a DRC and a LVS.

 

 

 

Then the 8-bit version of the AND gate was created using the individual AND gate cell.

 

 

Here is the DRC result for the 8-bit AND gate.

 

 

 The layout was extracted and a LVS ran, which succeeded.

 

 

Now on to the OR gate. First, the single gate.

 

 

 This passes a DRC and a LVS.

 

 Then the 8-bit OR gate made using the individual OR gate cells.  

   

 

This passes a DRC.

 

 

 It also passes a LVS.
 

 

Now we then move on the the multiplexer. Here is the individual gate.

 

 

 This passes a DRC and LVS.

 

 

The 8-bit version was then made, although it has an inverter that generates the complementary select signal, which is on the left of the layout below.

 

  

This passes a DRC.

 

 

 After extracting the layout, I ran a LVS, which passed.

 

With all of the individual component layouts completed, I made the full layout for the ALU. This can be seen in full below.

 

It is hard to make out what is going on in that image, so a labeled version is below. Note that all the VDD and GND nets of the individual components are tied together in several places and with large wires. The AND and OR gates are placed above the adder in order to make the design more compact. All of the inputs are at the top and the outputs are all at the bottom right.

 

 

Now to ensure that there are no rule violations, I ran a DRC.

 

 Passing that, I extracted the layout, setup and ran a LVS, which succeeded.

 

 

 And with that, the project has been completed. The finished project can be downloaded here.

 

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