Lab 7 - EE 421L 

Authored by Brian Smith (smith945@unlv.nevada.edu),

October 27th, 2014

In this lab, we made the 8-bit gate schematics for the ALU project as well as simulations for them, and an 8-bit adder schematic and layout.

First, here is the and gate schematic.

Then the symbol for that.

Then a schematic for the 8-bit combination.

The the symbol for that.

Now for the inverter. Here is the schematic.

And the symbol.

Then the schematic for a 4-bit inverter to test.

Then a symbol for that.

Then a simulation for it.

Here are the simulation settings for that.

And here is the output.

Then I made a schematic for an 8-bit group of inverters.

Then the symbol for it.

Then a multiplexer is made. Here is the schematic for it.

Then I made a symbol for it.

Then I made a NAND gate schematic.

And a symbol for it.

And a schematic for an 8-bit group of them.

Then a symbol for it.

Now for a NOR gate schematic.

I made a symbol for that as well.

Now for an 8-bit group of them.

Then I made a symbol for that.

Then I simulated them using the following schematic.

Here are the simulation settings for doing that.

The output of this is shown below.

Then I made a schematic for a full adder shown in figure 12.20.

Here is a symbol for that.

Here is a symbol for an 8-bit group of them.

Here is an symbol for that.

And that concludes this laboratory assignment. My lab7 directory is backed up here.

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