Lab 6 - EE 421L 

Authored by Brian Smith (smith945@unlv.nevada.edu),

October 20th, 2014

The goal of this lab is to create the layout, schematic, and symbol for a NAND gate, an XOR gate, and a full adder.

To start, I made the schematic for the NAND gate, shown below.

Then I made the schematic for the XOR gate.

Then I made the layout for the NAND gate.

Then the layout for the XOR gate.

Then I made the symbols for each. Here is the NAND gate symbol.

Then the XOR gate symbol.

Now, after a successful DRC and after extracting the layout, I set up a LVS for the NAND gate with the settings shown below.

This successfully completed, with the output shown below.

Then, after a successful DRC and after extracting the layout, I set up a LVS for the XOR gate.

Once again, this ran successfully. The output is shown below.

With the two gates completed, I made a schematic to test it. This shematic is shown below. The voltage sources are set up to make the inputs, AB, 00, 01, 10, 11.

I set up the simulation as shown below.

The models need to be included, so that was done.

The simulation was run. The output is below.

Now to make a full adder using those gates. This is the schematic needed.

Then I made a layout by placing the gates end to end and routing metal layers to make the needed connections.

With that succesfully passing a DRC, I then made a symbol for it.

Then extracted the layout and I ran a LVS. The setup for that is below.

The schematic and extracted views matched. Here is the output.

That concludes laboratory 6. My library backup for this lab is located here.

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