Lab 4 - EE 421L 

Authored by Brian Smith (smith945@unlv.nevada.edu),

October 6th, 2014

In this lab, I simulated NMOS and PMOS transistor to show some of their characteristics, as well as created a layout for the simulated transistors.

To start off, I created a schematic to simulate ID vs. VDS of a NMOS transistor with VDS going from 0V to 5V in 1mV increments for VGS being 0V to 5V in 1V increments. The schematic is shown below.

The NMOS used is using the SPICE model for the mosfets used in the C5 process. I set this up by changing the name of the model name in the schematic and adding the file with the models to the Model Library Setup window in the ADE program. This can be seen in the next two images.

First, I set up VDS to vary from 0V to 5V in the ADE with a DC sweep.

Then, inside of the parametric analysis tool, I set the VGS variable to sweep from 0V to 5V in 1V increments, as shown below.

Running the analysis gives us the following output.  Note that each line is a different value of VGS, seen on the left in the VGS column.

Next I made a schematic to simulate ID vs. VGS as VGS goes from 0V to 2V in 1mV increments, with VDS equal to 100mV, this time using a 4 terminal device.

Here, all that we need to do is set VGS to sweep from 0V to 2V in 1mV increments.

Doing this gives us the following output.

For the next analysis, I made a schematic to simulate a PMOS transistor for ID vs. VSD as we also vary VSG.

As in the last two simulations, I used a model of the C5 process, this time for a PMOS transistor. I did this the same way, as shown before in the transistor parameters.

As before, first I set up a DC sweep, this time for VSD, to go from 0V to 5V.

Also similar to the first simulation, I ran a parametric sweep over VSG as well.

Running this gave the following result.

For the last simulation, I simulated ID vs. VSG with VSD being 100mV. To do this, I made a schematic similar to the previous one, but using a 4 terminal PMOS in place of the 3 terminal symbol.

I then ran a DC sweep on VSG from 0V to 2V in 1mV increments as shown below.

This is the output of running that analysis.

After doing that, I moved on to making layouts for the 6u/600n NMOS and 12u/600n PMOS used in the schematics in the C5 process. I started by making a schematic, layout and symbol for a probe pad to simplify the process.

The following probe pad was made using the minimum overglass area rounded up to the nearest 0.3um, which is 20.1um. The metal needs to overlap the overglass by 6um, which makes the metal 32.1um x 32.1um. 

Then I made a schematic for the NMOS so that I could LVS the layout. This is shown below.

With that done, I made a layout for the device. I used the NCSU NMOS parametric model with the needed parameters entered. I added contacts and vias to get up to metal3, so that I could connect with the probe pads. I labeled the pins as I did in the schematic.

I connected the pins to 4 instances of the probe pads previously created.

I then ran a DRC, which succeeded as shown below.

I then extracted the layout and set up an LVS to run.

This successfully ran and had no errors in the output, shown below.

Lastly, I created a layout for the PMOS. I made a schematic for it so that I can LVS my layout.

I then created a layout of the PMOS. I used the PMOS parametric model with my width and length parameters entered. I then made pins to conform to the schematic and used contacts, vias, metal1, and metal2 to get up to metal3 so that I could connect to the probe pads. The body of the PMOS is connected to the n-well that the PMOS is in.

The DRC for this layout succeeded.

Then I extracted the layout and set up an LVS.

This successfully ran with no errors in the output.

And that concludes this laboratory assignment. My lab4 directory is backed up here.

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