Lab 3 - EE 421L 

 Authored by Brian Smith (smith945@unlv.nevada.edu),

 29 September 2014

To start out, I made a 10k resistor in the C5 Process. I used a width of 4.5um as in the tutorial and calculated the needed length with R = Rsq * L/W = (800)*L/(4.5) = 10k or L = 56.25um. Because everything needs to line up with a half lambda (0.15um) grid, I rounded that down to 56.1um. I then added some contacts to the end connecting to metal1. So that the extracted view will interpret my resistor as being a resistor, I put a res_id layer above where my resistor was laid out. Finally, I created metal1 pins, labeled "L" and "R", for the left and right sides. 
 

 
After doing a DRC on the layout to be sure that I made no errors, I extracted the layout to confirm that the resistance is near what I calculated. As you can see in the extracted view below, it was close at about 10.2K ohms.
 

   
Now, I moved to creating a layout for the resistor divider to be used in the DAC layout. I started by creating 3 instances of the resistor layout just created. I then joint the 3 resistors together with metal1 and created metal1 pins with names to match the resistor divider schematic. After a successful DRC, this is the result:
 

 
Now I extracted the layout and ran a LVS with the following settings.
 

 
The netlists matched, but to be sure everything is right, I checked the output.
 

 
Having no problems with the output, I moved on to creating the final and full layout for the DAC. I made 10 instances of the resistor divider layout and one 10k ohm resistor layout instance. I then used metal1 to connect the pins to conform with the DAC schematic that I had previously created. To finish I created pins with metal1 to conform with the schematic for my DAC, making sure the set the pins as input or output appropriately. Throughout all of this, I was mindful of the minimum spacing requirements.
 

 
 
As before, I successfully completed the DRC, extracted the layout, and set up a LVS as shown below:
 

 
After that successfully completed, I checked the output to be sure that there were no other problems.
 

 
This completes this laboratory assignment. The zipped lab folder can be found here.
 

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