Lab 2 - EE 421L 

 Authored by Brian Smith (smith945@unlv.nevada.edu),

 15 September 2014

Prelab:

Before going to the lab, I had to open up a simulation of sinusoidal voltage source going through an ADC then a DAC. After getting the file off of CMOSedu.com, I uploaded it to the working directory I am using for Cadance, unzipped it and added the library to the "cds.lib" file. Starting cadance, I loaded the schematic contained within the library to get the following:

Opening up ADE L and loading the saved state, I ran the simulation. This gave me the following:
 

 
 This circuit works taking the input signal, in this case a sinusoid with a magnitude of 2.5V and offset by 2.5V, and putting it through the ADC then a DAC. The ADC outputs a 10 wires, each representing 1 bit, being 5V when on and 0V when off. The 10 bit output of the ADC represents 2^10 discrete levels from 0V to 5V with 5/2^10 = ~4.88mV per level. The DAC takes the 10 bits and creates a signal from them by outputting the discrete voltage level represented by the 10 bits. The least significant bit is either B9 or B0. Which bit it is can be found by measuring both. Since the max level of 5V is represented by the biggest binary number, 1111111111, the most significant bit will be 5V when the input is at or above about 2.5V while the least significant bit will change often as it represents every other discrete voltage level. Here is the plot of the input and B9:
 

 
 It follows what I expected of the most significant bit, so B0 must be the least significant bit.
 
 Laboratory Report:
In this lab, I used resistors to make a 10-bit DAC. I made it based off the following schematic:
 
 
 
The output resistance of our circuit with B0-B9 can be found by putting all the switches to ground  along with the power and looking in from the load. By starting from the bottom 2R and 2R resistor, we work our way up, simplifying the parallel resistors then adding with the R resistor to make one more 2R resistor and repeating to the top, where there is just a parallel 2R and 2R, which simplifies to the total output resistance of R.
 
I started making our 10-bit DAC by making a cell for a resistive divider to make the overall circuit less complicated. This is what that looks like:
 

 
 I then made a symbol for this, seen below:
 

 
 After the symbol and circuit were finished, I wired them as in the original ideal DAC seen in the prelab, minus a few unused pins:
 

 
 Finishing my DAC, I made a symbol by copying the ideal DAC symbol into my cell and removing the unused pins.
 

 
With that complete, I made a new cell to test out the delay of the component if a 10pF capacitor was at the load and B9 was transitioned from 0V to 5V (VDD).
 
 

 
 
 
Lastly, I simulated the circuit from the pre-lab with the DAC replaced with my DAC as shown below.
 

 
 And here is the output of the simulation:
 

 
If the switches have a resistance that isn't small compared to R, then the output resistance will go up, making any capacitive load take longer to charge, increasing the delay of the circuit. It will also lower the output voltage.
 
Finally, there is the load. If it is resistive, then the ADC, which acts as a resistive divider, will have it's lower resistance lowered, making the output voltage scaled down for all inputs. If the load is capacitive, we have the same problem, but we also have a phase delay as well as the output being smoothed due to the charging and discharging. With both, we have the smoothing and delay effects, but because they are in parallel, the impedance of the load is lower, so the output is not attenuated as much.
 
Here is the circuit with a load of 10k ohms:

 

 
Here is the circuit with 10k ohms and 10pF in parallel:

 

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